Acknowledgment

¾ Clock delay and skew minimization are two important objectives in high speed VLSI circuit design. Buffer insertion has been used as an effective approach to achieve both minimal delay and skew. In this paper, we present a buffer insertion algorithm for optimizing highspeed clock tree. For a given wiring tree, the algorithm inserts the same number of buffers along every source-tosink path, such that both path delay and skew are optimized. After buffer insertion, each subtree rooted at the source or each buffer has almost the same average delay. This property helps to reduce signal delay and skew sensitivity due to process variations. Elmore delay model is used in our optimization procedure which provides a more accurate delay evaluation than that the simple wire length model does. The simulated annealing method is used in our algorithm to find the optimal buffer positions. I. INTRODUCTION With the remarkable evolution of VLSI technology, clock delay and skew minimization have become ..