High-Speed Area-Efficient Implementation of AES Algorithm on Reconfigurable Platform

Nowadays, digital information is very easy to process, but it allows unauthorized users to access to this information. To protect this information from unauthorized access, cryptography is one of the most powerful and commonly used techniques. There are various cryptographic algorithms out of which advanced encryption standard (AES) is one of the most frequently used symmetric key cryptographic algorithms. The main objective of this chapter is to implement fast, secure, and area-efficient AES algorithm on a reconfigurable platform. In this chapter, AES algorithm is designed using Xilinx system generator, implemented on Nexys-4 DDR FPGA development board and simulated using MATLAB Simulink. Synthesis results show that the implementation consumes 121 slice registers, and its maximum operating frequency is 1102.536 MHz. Throughput achieved by this implementation is 14.1125 Gbps

Watermarking and Cryptography Based Image Authentication on Reconfigurable Platform

Now-a-days, multimedia based applications have been developed rapidly. Digital information is easy to process but it allows illegal users to access the data. For protecting the data from this illegal use, Digital Rights Management (DRM) can be used. DRM allows secure exchange of digital data over internet or other electronic media. In this paper, FPGA based implementation of DWT alongwith Advanced Encryption Standard (AES) based watermarking is discussed. With this approach, improved security can be achieved. The complete system is designed using HDL and simulated using Questasim and MATLAB Simulink model. The synthesis result shows that this implementation occupies only 2117 slices and maximum frequency reported for this design is 228.064 MHz