A systemic analysis of silicon substrates toward improvements of integrated FD-SOI circuits performance at mm-wave frequencies

The emergence and deployment of new telecommunication standards (5G then 6G) requires low-cost, high RF performance and high integration density technologies. Fully-depleted-Silicon-on-Insulator (FD-SOI) technology is ideally placed in this context, thanks to best-in-class RF performance among CMOS, low-cost, high-volume manufacturability and intrinsic advantages enabling additional configurability. This thesis adopts a systemic and parallel approach to analyze the substrate effect on integrated circuits (ICs) working at millimeter-wave (mm-wave) frequencies. In the first part, the constituting elements of ICs (substrate, active and passive elements) are studied separately, and their sensitivity to the substrate properties is analyzed. Some specific on-wafer measurement aspects are also investigated to improve the measurement accuracy. Then, building on the accumulated knowledge, the last part addresses the substrate impact at the mm-wave IC level. Overall, this thesis demonstrates that enhancing the RF substrate quality in an FD-SOI technology can lead to substantial improvement of passives and circuits at mm-wave frequencies, and therefore paves the way for potential adoption of high-resistivity substrates in future industrial UTBB FD-SOI technology.(FSA - Sciences de l'ingénieur) -- UCL, 202

Low loss Si-substrates enhanced using buried PN junctions for RF applications

A novel method for increasing the effective resistivity in low-doped silicon substrates is presented. By creating a chain series of p-n depletion junctions beneath the insulator, the parasitic surface conduction channel is interrupted, significantly lowering substrate losses and reducing harmonic distortion in the simulated and measured CPW lines achieving performance close to the widely used trap-rich silicon substrate at RF frequencies

Assessment of RF compact modelling of FD SOI transistors

In this work, the compact model for FD SOI transistors and its limitations are assessed by comparing Spectre simulations to experimental measurements in a wide range of frequencies the impact of two phenomena, namely self-heating (SH) and substrate effect (SE), on the frequency response of output conductance and capacitance and their respective modelling are studied. This work shows that the present version of compact model is not sufficient to accurately model the experimentally observed transitions in the output conductance and capacitance frequency response related to these two phenomena

Effect of probe coupling on MOSFET series resistance extraction up to 110 GHz

The measurement of series extrinsic resistances of MOSFETs is not straightforward and the gate resistance (Rg) in particular is very sensitive to noise measurement and measurement inaccuracies. They are critical elements that need an accurate estimation for proper FET modeling and RF figures of merit assessment, as they limit the extrinsic cutoff and maximum oscillation frequencies (ft, fmax) in deeply scaled CMOS technologies. This work compares the extrinsic resistances extraction with different off-wafer and on-wafer calibration and de-embedding methods to provide an insight on the appropriate procedure for accurate correction. Then, measurements obtained with three different probe technologies are compared. A resonance-like signature specific to each probe technology is observed, caused by unwanted coupling between the probe and the on-chip neighbor environment of the test structures. This coupling is not well corrected by the calibration and de-embedding procedure and is reflected back on the corrected measurements, mainly on the fmax and Rg curves. Overall, the best probe technology for DC-110 GHz measurements among the probes tested in this work is identified to be Picoprobe, featuring a gate resistance extraction with less than ±3% variation from 10 to 60 GHz

Voluntas Symposium: Comments on Salamon and Sokolowski’s Re-conceptualization of the Third Sector

With their “Beyond Nonprofits: Re-conceptualizing the Third Sector”, Salamon and Sokolowski have made an important contribution to the ongoing debate on how to define the third sector. This Voluntas symposium brings together the comments of five leading scholars both supportive and critical of the new definition. The comments are based on a debate held at the conference of the International Society for Third Sector Research, in Stockholm in 2016

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

This paper proposes an original approach to separately characterize self-heating and substrate effects in Fully-Depleted Silicon-on-Insulator (FD-SOI) devices. As both dynamic self-heating and drain to source coupling through the back-gate and substrate of an FD-SOI MOSFET induce a frequency transition in the Y-parameters in a common frequency range, it is crucial to properly separate them for further modeling. The proposed novel method is based on the extraction of the back-gate and substrate networks from the S-parameters measured at the zero-temperature coefficient bias. It enables the accurate and unambiguous extraction of thermal impedance for different biases, thus providing the extraction of the device thermal resistance and capacitance for different power levels from S-parameters measurements

DC-40 GHz SPDTs in 22 nm FD-SOI and Back-Gate Impact Study

In this paper, ultra-wideband SPDTs fabricated in the 22 nm FD-SOI process from GLOBALFOUNDRIES are presented. Three SPDT modules were implemented, each using a different type of millimeter-wave NFET, namely a conventional-well regular-V t (RVT) device, a flipped-well super-low-V t (SLVT) device and a specially treated device without back-gate well contact for decreased substrate parasitics (BFMOAT device). It is shown that using the back-gate achieves lower losses, higher isolation and better linearity for the RVT and SLVT based switches, while the reduced parasitic BFMOAT switch shows better performance at the high-end of the mm-wave spectrum

High-Resistivity substrates with PN interface passivation in 22 nm FD-SOI

In this paper, GlobalFoundries’ 22 nm FD-SOI process was run on standard and high-resistivity wafers evaluating a PN junction interface passivation solution to counter parasitic surface conduction (PSC) effects. Substrate quality was monitored in terms of losses, effective resistivity (ρeff) and generated harmonics through on-wafer measurements of coplanar waveguides (CPW), fabricated in either bottom metal or in top metal layers. The PN patterns demonstrate effective passivation of the PSC, enabling ρeff values in the kΩcm range. Patterns with bias contacts were fabricated, demonstrating substantial increase in ρeff when applying a reverse bias to widen the depletion regions. PN grid patterns also exhibit good RF performance results, and are attractive since they alleviate layout/PN pattern co-design