BEOL Thermal Resistance Extraction in SiGe HBTs

A prior estimate of the impact of thermal resistance from the back-end-of-line (BEOL) metallization layers is crucial for an accurate circuit design and thermally aware device design. This paper presents a robust technique to extract the thermal resistance component originating from the BEOL metal layers in silicon germanium heterojunction bipolar transistors (SiGe HBTs). The proposed technique is first tested on data generated using analytical equations and later validated with 3D TCAD simulation. The results clearly show that the exact contribution of the BEOL to the overall thermal resistance is captured in the proposed approach. Finally, we verified the method using measured data obtained from fabricated SiGe HBT structures using Infineon B11HFC technology. The extracted parameters show reasonable accuracy and consistency across different emitter dimensions and BEOL configurations

The HotSpot compensation in high speed data converters

by Satyajit Mohapatra and Nihar Ranjan Mohapatr

A computationally efficient quantum-corrected poisson solver for accurate device simulation of multi-gate FETs

The quantum mechanical effects have become an important phenomenon in extremely scaled multi-gate MOS devices and therefore the self-consistent solution of Poisson�s and Schrodinger�s equation (P-S solver) is needed to get accurate charge and potential profiles. The commercial device simulators take impractically high computation time for the P-S solver. So, there is a need for a computationally efficient methodology which is fast as well as accurate. In this paper, a quantum corrected Poisson solver is developed which serves this purpose. The effects of quantum confinement due to geometry of the device and the electric field are captured accurately by modifying the density of states and incorporating correction in carrier charge profiles. The developed model is physics-based, accurate, and computationally efficient in comparison to the existing quantum correction models.by Apoorva Ojha and Nihar R. Mohapatr

A computationally efficient compact model for trap-assisted carrier transport through multi-stack gate dielectrics of HKMG nMOS transistors

This paper analyzes in detail the carrier transport through the multi stack gate dielectric of High-K Metal gate (HKMG) nMOS transistors under different gate biases and temperatures. The existing uncertainty about the carrier transport mechanisms for different gate biases is resolved through accurate band diagram analysis and gate current measurement under different conditions. The Trap Assisted Tunneling (TAT, elastic and inelastic) and Poole-Frenkel (PF) conduction are identified as the two dominant mechanisms of carrier transport. These two mechanisms are found to be prevalent in different gate bias ranges and have distinct signatures. A computationally efficient compact model for the gate current in HKMG nMOS transistors is developed capturing the simultaneity of both the carrier transport mechanisms. The proposed model is valid for all gate voltages (accumulation to inversion) and for different temperatures. The accuracy of the proposed model is confirmed by comparing it with the experimental data.by Apoorva Ojha and Nihar R.Mohapatr

Mismatch resilient 3.5-Bit MDAC with MCS-CFCS

by Satyajit Mohapatra, Hari Shanker Gupta and Nihar Ranjan Mohapatr

Effects of Small Geometries on the Performance of Gate First High- \kappa Metal Gate NMOS Transistors

This paper discusses in detail the effect of small geometries on the performance of NMOS transistors fabricated using a 28-nm gate-first CMOS technology. It is shown that the threshold voltage and transconductance of the NMOS transistors increase with the decrease in the channel width, and this effect is enhanced at shorter gate lengths. PMOS transistors show conventional width dependence. The possible physical mechanisms responsible for this anomalous behavior are identified and explained through detailed measurements. A 2-D charge-distribution-based model is proposed to model this anomalous effect. The accuracy of the proposed model is verified by comparing it with the experimental and simulated data.by Amey Walke and Nihar Ranjan Mohapatr

Trap-assisted carrier transport through the multi-stack gate dielectrics of HKMG nMOS transistors: a compact model

In this paper, a compact model for the gate current in HKMG nMOS transistors is presented. The carrier transport through the multi-stack gate dielectrics of HKMG MOS transistors is shown to be dominated by the Trap Assisted Tunneling and Poole-Frenkel conduction mechanisms. Both these mechanisms occur simultaneously and each is dominant in a particular gate voltage range. The interdependence and simultaneity of both the mechanisms is modeled to get a compact gate current formulation. The model is valid for all gate voltages and for different temperatures. The model also includes the formulation of inelastic TAT in a compact format. The accuracy of the model is validated with the measurement data.by Apoorva Ojha and Nihar Ranjan Mohapatr

Analysis and modeling of the marrow width effect in gate-first HKMG nMOS transistors

This paper analyzes and models the narrow width effect (NWE) observed in nMOS transistors fabricated using a 28-nm gate-first CMOS process. It is shown that the threshold voltage of nMOS transistors increases with decrease in channel width and this effect is enhanced at shorter gate lengths, thicker hafnium oxide (HfO₂), and thicker lanthanum (La) capping layer. It is also observed that this increase in threshold voltage for narrow width transistors is influenced by the device layout. The physical mechanisms responsible for the observed anomalous behavior are identified through measurements on different test structures. An empirical model is proposed to understand and model this behavior. The accuracy of the model is verified by comparing it with the experimental data. It is finally proposed that the observed NWE could be minimized by optimizing the thickness of HfO₂, La capping layer, and SiO₂ interfacial layer and by using different device layouts.by Satya M. Sivanaresh and Nihar Ranjan Mohapatr