Photon Counting Using Edge-Detection Algorithm

New applications such as high-datarate, photon-starved, free-space optical communications require photon counting at flux rates into gigaphoton-per-second regimes coupled with subnanosecond timing accuracy. Current single-photon detectors that are capable of handling such operating conditions are designed in an array format and produce output pulses that span multiple sample times. In order to discern one pulse from another and not to overcount the number of incoming photons, a detection algorithm must be applied to the sampled detector output pulses. As flux rates increase, the ability to implement such a detection algorithm becomes difficult within a digital processor that may reside within a field-programmable gate array (FPGA). Systems have been developed and implemented to both characterize gigahertz bandwidth single-photon detectors, as well as process photon count signals at rates into gigaphotons per second in order to implement communications links at SCPPM (serial concatenated pulse position modulation) encoded data rates exceeding 100 megabits per second with efficiencies greater than two bits per detected photon. A hardware edge-detection algorithm and corresponding signal combining and deserialization hardware were developed to meet these requirements at sample rates up to 10 GHz. The photon discriminator deserializer hardware board accepts four inputs, which allows for the ability to take inputs from a quadphoton counting detector, to support requirements for optical tracking with a reduced number of hardware components. The four inputs are hardware leading-edge detected independently. After leading-edge detection, the resultant samples are ORed together prior to deserialization. The deserialization is performed to reduce the rate at which data is passed to a digital signal processor, perhaps residing within an FPGA. The hardware implements four separate analog inputs that are connected through RF connectors. Each analog input is fed to a high-speed 1-bit comparator, which digitizes the input referenced to an adjustable threshold value. This results in four independent serial sample streams of binary 1s and 0s, which are ORed together at rates up to 10 GHz. This single serial stream is then deserialized by a factor of 16 to create 16 signal lines at a rate of 622.5 MHz or lower for input to a high-speed digital processor assembly. The new design and corresponding hardware can be employed with a quad-photon counting detector capable of handling photon rates on the order of multi-gigaphotons per second, whereas prior art was only capable of handling a single input at 1/4 the flux rate. Additionally, the hardware edge-detection algorithm has provided the ability to process 3-10 higher photon flux rates than previously possible by removing the limitation that photoncounting detector output pulses on multiple channels being ORed not overlap. Now, only the leading edges of the pulses are required to not overlap. This new photon counting digitizer hardware architecture supports a universal front end for an optical communications receiver operating at data rates from kilobits to over one gigabit per second to meet increased mission data volume requirements

Goldstone Solar System Radar Waveform Generator

Due to distances and relative motions among the transmitter, target object, and receiver, the time-base between any transmitted and received signal will undergo distortion. Pre-distortion of the transmitted signal to compensate for this time-base distortion allows reception of an undistorted signal. In most radar applications, an arbitrary waveform generator (AWG) would be used to store the pre-calculated waveform and then play back this waveform during transmission. The Goldstone Solar System Radar (GSSR), however, has transmission durations that exceed the available memory storage of such a device. A waveform generator capable of real-time pre-distortion of a radar waveform to a given time-base distortion function is needed. To pre-distort the transmitted signal, both the baseband radar waveform and the RF carrier must be modified. In the GSSR, this occurs at the up-conversion mixing stage to an intermediate frequency (IF). A programmable oscillator (PO) is used to generate the IF along with a time-varying phase component that matches the time-base distortion of the RF carrier. This serves as the IF input to the waveform generator where it is mixed with a baseband radar waveform whose time-base has been distorted to match the given time-base distortion function producing the modulated IF output. An error control feedback loop is used to precisely control the time-base distortion of the baseband waveform, allowing its real-time generation. The waveform generator produces IF modulated radar waveforms whose time-base has been pre-distorted to match a given arbitrary function. The following waveforms are supported: continuous wave (CW), frequency hopped (FH), binary phase code (BPC), and linear frequency modulation (LFM). The waveform generator takes as input an IF with a time varying phase component that matches the time-base distortion of the carrier. The waveform generator supports interconnection with deep-space network (DSN) timing and frequency standards, and is controlled through a 1 Gb/s Ethernet UDP/IP interface. This real-time generation of a timebase distorted radar waveform for continuous transmission in a planetary radar is a unique capability

Optical Communications Channel Combiner

NASA has identified deep-space optical communications links as an integral part of a unified space communication network in order to provide data rates in excess of 100 Mb/s. The distances and limited power inherent in a deep-space optical downlink necessitate the use of photon-counting detectors and a power-efficient modulation such as pulse position modulation (PPM). For the output of each photodetector, whether from a separate telescope or a portion of the detection area, a communication receiver estimates a log-likelihood ratio for each PPM slot. To realize the full effective aperture of these receivers, their outputs must be combined prior to information decoding. A channel combiner was developed to synchronize the log-likelihood ratio (LLR) sequences of multiple receivers, and then combines these into a single LLR sequence for information decoding. The channel combiner synchronizes the LLR sequences of up to three receivers and then combines these into a single LLR sequence for output. The channel combiner has three channel inputs, each of which takes as input a sequence of four-bit LLRs for each PPM slot in a codeword via a XAUI 10 Gb/s quad optical fiber interface. The cross-correlation between the channels LLR time series are calculated and used to synchronize the sequences prior to combining. The output of the channel combiner is a sequence of four-bit LLRs for each PPM slot in a codeword via a XAUI 10 Gb/s quad optical fiber interface. The unit is controlled through a 1 Gb/s Ethernet UDP/IP interface. A deep-space optical communication link has not yet been demonstrated. This ground-station channel combiner was developed to demonstrate this capability and is unique in its ability to process such a signal

Sample-Clock Phase-Control Feedback

To demodulate a communication signal, a receiver must recover and synchronize to the symbol timing of a received waveform. In a system that utilizes digital sampling, the fidelity of synchronization is limited by the time between the symbol boundary and closest sample time location. To reduce this error, one typically uses a sample clock in excess of the symbol rate in order to provide multiple samples per symbol, thereby lowering the error limit to a fraction of a symbol time. For systems with a large modulation bandwidth, the required sample clock rate is prohibitive due to current technological barriers and processing complexity. With precise control of the phase of the sample clock, one can sample the received signal at times arbitrarily close to the symbol boundary, thus obviating the need, from a synchronization perspective, for multiple samples per symbol. Sample-clock phase-control feedback was developed for use in the demodulation of an optical communication signal, where multi-GHz modulation bandwidths would require prohibitively large sample clock frequencies for rates in excess of the symbol rate. A custom mixedsignal (RF/digital) offset phase-locked loop circuit was developed to control the phase of the 6.4-GHz clock that samples the photon-counting detector output. The offset phase-locked loop is driven by a feedback mechanism that continuously corrects for variation in the symbol time due to motion between the transmitter and receiver as well as oscillator instability. This innovation will allow significant improvements in receiver throughput; for example, the throughput of a pulse-position modulation (PPM) with 16 slots can increase from 188 Mb/s to 1.5 Gb/s

Programmable Oscillator

A programmable oscillator is a frequency synthesizer with an output phase that tracks an arbitrary function. An offset, phase-locked loop circuit is used in combination with an error control feedback loop to precisely control the output phase of the oscillator. To down-convert the received signal, several stages of mixing may be employed with the compensation for the time-base distortion of the carrier occurring at any one of those stages. In the Goldstone Solar System Radar (GSSR), the compensation occurs in the mixing from an intermediate frequency (IF), whose value is dependent on the station and band, to a common IF used in the final stage of down-conversion to baseband. The programmable oscillator (PO) is used in the final stage of down-conversion to generate the IF, along with a time-varying phase component that matches the time-base distortion of the carrier, thus removing it from the final down-converted signal

DOT Transmit Module

The Deep Space Optical Terminal (DOT) transmit module demonstrates the DOT downlink signaling in a flight electronics assembly that can be qualified for deep space. The assembly has the capability to generate an electronic pulse-position modulation (PPM) waveform suitable for driving a laser assembly to produce the optical downlink signal. The downlink data enters the assembly through a serializer/ deserializer (SERDES) interface, and is encoded using a serially concatenated PPM (SCPPM) forward error correction code. The encoded data is modulated using PPM with an inter-symbol guard time to aid in receiver synchronization. Monitor and control of the assembly is via a low-voltage differential signal (LVDS) interfac

Downsampling Photodetector Array with Windowing

In a photon counting detector array, each pixel in the array produces an electrical pulse when an incident photon on that pixel is detected. Detection and demodulation of an optical communication signal that modulated the intensity of the optical signal requires counting the number of photon arrivals over a given interval. As the size of photon counting photodetector arrays increases, parallel processing of all the pixels exceeds the resources available in current application-specific integrated circuit (ASIC) and gate array (GA) technology; the desire for a high fill factor in avalanche photodiode (APD) detector arrays also precludes this. Through the use of downsampling and windowing portions of the detector array, the processing is distributed between the ASIC and GA. This allows demodulation of the optical communication signal incident on a large photon counting detector array, as well as providing architecture amenable to algorithmic changes. The detector array readout ASIC functions as a parallel-to-serial converter, serializing the photodetector array output for subsequent processing. Additional downsampling functionality for each pixel is added to this ASIC. Due to the large number of pixels in the array, the readout time of the entire photodetector is greater than the time between photon arrivals; therefore, a downsampling pre-processing step is done in order to increase the time allowed for the readout to occur. Each pixel drives a small counter that is incremented at every detected photon arrival or, equivalently, the charge in a storage capacitor is incremented. At the end of a user-configurable counting period (calculated independently from the ASIC), the counters are sampled and cleared. This downsampled photon count information is then sent one counter word at a time to the GA. For a large array, processing even the downsampled pixel counts exceeds the capabilities of the GA. Windowing of the array, whereby several subsets of pixels are designated for processing, is used to further reduce the computational requirements. The grouping of the designated pixel frame as the photon count information is sent one word at a time to the GA, the aggregation of the pixels in a window can be achieved by selecting only the designated pixel counts from the serial stream of photon counts, thereby obviating the need to store the entire frame of pixel count in the gate array. The pixel count se quence from each window can then be processed, forming lower-rate pixel statistics for each window. By having this processing occur in the GA rather than in the ASIC, future changes to the processing algorithm can be readily implemented. The high-bandwidth requirements of a photon counting array combined with the properties of the optical modulation being detected by the array present a unique problem that has not been addressed by current CCD or CMOS sensor array solutions

Scalable SCPPM Decoder

A decoder was developed that decodes a serial concatenated pulse position modulation (SCPPM) encoded information sequence. The decoder takes as input a sequence of four bit log-likelihood ratios (LLR) for each PPM slot in a codeword via a XAUI 10-Gb/s quad optical fiber interface. If the decoder is unavailable, it passes the LLRs on to the next decoder via a XAUI 10-Gb/s quad optical fiber interface. Otherwise, it decodes the sequence and outputs information bits through a 1-GB/s Ethernet UDP/IP (User Datagram Protocol/Internet Protocol) interface. The throughput for a single decoder unit is 150-Mb/s at an average of four decoding iterations; by connecting a number of decoder units in series, a decoding rate equal to that of the aggregate rate is achieved. The unit is controlled through a 1-GB/s Ethernet UDP/IP interface. This ground station decoder was developed to demonstrate a deep space optical communication link capability, and is unique in the scalable design to achieve real-time SCPP decoding at the aggregate data rate

Threshold-based wireless-based NOMA systems over log-normal channels: Ergodic outage probability of joint time allocation and power splitting schemes

Due to the development of state-of-the-art fifth-generation communication (5G) and Internet-of-Things (IoT), the demands for capacity and throughput of wireless networks have increased significantly. As a promising solution for this, a radio access technique, namely, non-orthogonal multiple access (NOMA) has been investigated. Particularly, in this paper, we analyse the system performance of a joint time allocation and power splitting (JTAPS) protocol for NOMA-based energy harvesting (EH) wireless networks over indoor scenarios, which we modelled with log-normal fading channels. Accordingly, for the performance analysis of such networks, the analytical expression of a metric so-called "ergodic outage probability" was derived. Then, thanks to Monte Carlo simulations done in Matlab, we are able to see how different EH power splitting (PS) and EH time switching (TS) factors influence the ergodic outage probability. Last, but not least, we plot the simulation results along with the theoretical results for comparison studies.Web of Science27