Resonant Frequency Characteristics of a SAW Device Attached to Resonating Micropillars

Recently we reported experimental and simulation results on an increase in resonance frequency of a SAW resonator caused by mass loading of micropillars made of SU-8, attached normal to the surface of the resonator. We concluded that SAW resonator and the SU-8 micropillars in unison form a system of coupled resonators. We have now extended this work and performed a finite element method simulation to study the resonance frequency characteristics of the SAW-based coupled resonator. In this paper we report the effect of the resonance frequency of the micropillars on the resonance frequency of the system of coupled resonators, and observe the coupling of micropillar resonance and the propagating SAW as described in the well known Dybwad system of coupled resonators

Replacement of conventional reference electrode with platinum electrode for electronic tongue based analysis of dairy products

This work demonstrates the utility of platinum metal electrode as replacement for conventional Ag/AgCl reference electrode for voltammetric electronic tongue based analysis of edible dairy products. It overcomes the limitations of conventional silver-based reference electrode that presents a potential health hazard when employed for analysis of edible dairy products. Various dairy products like toned milk, Lassi and skimmed milk powder were tested using a cluster of platinum, gold and rhodium working electrodes. Responses of electrode cluster were captured using cyclic voltammetry. Comparative investigations were carried out between responses with platinum reference electrode and Ag/AgCl reference electrode. Repeatability and reproducibility of results have been examined. Our results suggest that platinum metal reference electrode can be reliably used for voltammetric electronic tongue based analysis of dairy products. Further this shall pave way for commercial development of electronic tongue technology in food sector adhering to hygienic and food safety regulations

High performance multiplierless serial pipelined VLSI architecture for real-valued FFT

This paper presents a high-performance multiplierless serial pipelined architecture for real-valued fast Fourier transform (FFT). A new data mapping scheme (DMS) is suggested for the proposed serial pipelined FFT architecture. The performance is enhanced by performing FFT computations in log- 2 N-1 stages followed by a select-store-feedback (SSF) stage, where N is the number of points in FFT. Further enhancement in performance is achieved by employing quarter-complex multiplierless unit made up of memory and combinational logic in every stage. The memory stores half number of partial products while the remaining partial products are taken care by external combinational logic. Compared with the best existing scheme, the proposed design reduces the computational workload on half-butterfly (H-BF) units by (2N-8). Application specific integrated circuit (ASIC) and field programmable gate array (FPGA) results show that the proposed design for 1024-point achieves 31.54% less area, 30.13% less power, 33.56% less area-delay product (ADP), 27.11% less sliced look-up tables (SLUTs) and 28.37% less flip-flops (FFs) as compared to the best existing scheme.</p

An Efficient Implementation Approach to FFT Processor for Spectral Analysis

This article presents an efficient hardware implementation approach to a variable-size fast Fourier transform (FFT) processor for spectral analysis. Due to its capability to handle different frame sizes, it can be adapted in situations where operating parameters necessitate adhering to different standard requirements. A serial real-valued processor with a new data-flow graph is considered, as it requires the least number of multipliers. By joint use of stage-specific optimization and multiplierless structure, the overall hardware efficiency of the proposed design is enhanced. Clock gating is employed to enable the variable-size processor operation along with power reduction. A fixed-point (FP) analysis of the proposed design is considered. The proposed novel multiplierless structure is based on shift and accumulation (SA). This also includes the generation (and sharing) of partial products (PPs) based on their symmetries. The proposed design offers low area and low power as compared with the state of the art. It is demonstrated for spectral analysis of electroencephalogram (EEG) signals for machine-learning-based epileptic seizure prediction on a field-programmable gate array (FPGA) platform.</p

An Efficient Implementation Approach to FFT Processor for Spectral Analysis

This article presents an efficient hardware implementation approach to a variable-size fast Fourier transform (FFT) processor for spectral analysis. Due to its capability to handle different frame sizes, it can be adapted in situations where operating parameters necessitate adhering to different standard requirements. A serial real-valued processor with a new data-flow graph is considered, as it requires the least number of multipliers. By joint use of stage-specific optimization and multiplierless structure, the overall hardware efficiency of the proposed design is enhanced. Clock gating is employed to enable the variable-size processor operation along with power reduction. A fixed-point (FP) analysis of the proposed design is considered. The proposed novel multiplierless structure is based on shift and accumulation (SA). This also includes the generation (and sharing) of partial products (PPs) based on their symmetries. The proposed design offers low area and low power as compared with the state of the art. It is demonstrated for spectral analysis of electroencephalogram (EEG) signals for machine-learning-based epileptic seizure prediction on a field-programmable gate array (FPGA) platform.</p

Energy efficient VLSI architecture of real-valued serial pipelined FFT

This study presents an energy-efficient serial pipelined architecture of fast Fourier transform (FFT) to process real-valued signals. A new data mapping scheme is presented to obtain a normal order input-output without the requirement of a post-processing stage. It facilitates reduction in the computational workload on the hardware resources which is confirmed through mathematical derivations. Further, the proposed design involves a novel quadrant multiplier with relatively lower hardware complexity. It performs the quarter operation of a complex multiplier in one clock cycle, and thereby consumes relatively lower power. Moreover, in the last stage, a merged unit for butterfly computation and data re-ordering is also proposed which performs either a half-butterfly operation or interchanges data, and thereby reduces the hardware usage. Application specific integrated circuit synthesis and field programmable gate array results show that for a 1024-points FFT computation, the proposed architecture offers 10.26% savings in area, 20.83% savings in power, 16.98% savings in area-delay product and 26.76% savings in energy-per-sample, 7.79% savings in sliced look-up tables, and 11.93% savings in flip-flops over the best existing design.</p

An area and power-efficient serial commutator fft with recursive lut multiplier

This paper presents an area and power-efficient architecture for serial commutator real-valued fast Fourier transform (FFT) using recursive look-up table (LUT). FFT computation consists of butterfly operations and twiddles factor multiplications. The area and power performance of FFT architectures are mainly limited by the multipliers. To address this, a new multiplier is proposed which stores the partial products in LUT. Moreover, by adding the shifted version of twiddle coefficients, the stored partial products gain symmetry, and thus the size of LUT can be reduced to half. Further symmetry is achieved by adding another shifted version of twiddle coefficients and so on. This makes the proposed LUT multiplier recursive in nature. A new data management scheme is suggested for the proposed architecture. To validate the proposed architecture, application-specific integrated circuit (ASIC) synthesis and field-programmable gate array (FPGA) implementation are carried out for different symmetry factor. For instance, the proposed architecture for 1024-point with symmetry factor of two achieves 39.11% less area, 42.29% less power, 33.27% less sliced LUT (SLUT) and 29.18% less flip-flop (FF) as compared to the best existing design.</p