The Dynamics of Higher Education in Countries Experiencing Ethnic Conflict

My thesis investigates how higher education institutions influence and interact with students and professors, policymakers, the economy, and the general population following ethnic conflict. I use a mixed-method comparative analysis of universities in Kosovo, Sri Lanka, Sudan, and Turkey and an in-depth case study of Kosovo to analyze the dynamics of higher education in post-conflict environments. The majority of my research is drawn from personal interviews conducted between June 2017 and October 2017. I interviewed students, alumni, faculty, and administrators from Kosovo’s three most prominent universities: the University of Pristina, the University of Mitrovica, and the Rochester Institute of Technology Kosovo. The relationship between higher education and ethnic conflict can be broken down into four areas: ideology, language, intergroup contact, and the economy. Comparing universities in Kosovo, Sri Lanka, Sudan, and Turkey, reveals that higher education can be used as a means of marginalization by nationalists and the government. Fortunately, Sri Lanka, Turkey, and Kosovo, have, at least in part, also begun to use universities as a tool of recovery and reconciliation. In Kosovo, both public universities, the University of Mitrovica and the University of Pristina, struggle to overcome identity politics and reform at the pace the country needs. While RITK implements more effective teaching strategies and attempts to transcend ethnic boundaries, its small class size and high tuition limit its impact. Ultimately, the analysis suggests that those in charge of post-conflict reconstruction should prioritize rebuilding and reopening universities, assist public universities in reforming their curriculum, instructor training, and university policies, and reconstruct universities in a manner that intentionally encourages meaningful contact between ethnic groups

Doctor of Philosophy

dissertationWith the explosion of chip transistor counts, the semiconductor industry has struggled with ways to continue scaling computing performance in line with historical trends. In recent years, the de facto solution to utilize excess transistors has been to increase the size of the on-chip data cache, allowing fast access to an increased portion of main memory. These large caches allowed the continued scaling of single thread performance, which had not yet reached the limit of instruction level parallelism (ILP). As we approach the potential limits of parallelism within a single threaded application, new approaches such as chip multiprocessors (CMP) have become popular for scaling performance utilizing thread level parallelism (TLP). This dissertation identifies the operating system as a ubiquitous area where single threaded performance and multithreaded performance have often been ignored by computer architects. We propose that novel hardware and OS co-design has the potential to significantly improve current chip multiprocessor designs, enabling increased performance and improved power efficiency. We show that the operating system contributes a nontrivial overhead to even the most computationally intense workloads and that this OS contribution grows to a significant fraction of total instructions when executing several common applications found in the datacenter. We demonstrate that architectural improvements have had little to no effect on the performance of the OS over the last 15 years, leaving ample room for improvements. We specifically consider three potential solutions to improve OS execution on modern processors. First, we consider the potential of a separate operating system processor (OSP) operating concurrently with general purpose processors (GPP) in a chip multiprocessor organization, with several specialized structures acting as efficient conduits between these processors. Second, we consider the potential of segregating existing caching structures to decrease cache interference between the OS and application. Third, we propose that there are components within the OS itself that should be refactored to be both multithreaded and cache topology aware, which in turn, improves the performance and scalability of many-threaded applications

Neutron therapy of cancer

Reports relate applications of neutrons to the problem of cancer therapy. The biochemical and biophysical aspects of fast-neutron therapy, neutron-capture and neutron-conversion therapy with intermediate-range neutrons are presented. Also included is a computer program for neutron-gamma radiobiology

Interference aware cache designs for operating system execution

Journal ArticleLarge-scale chip multiprocessors will likely be heterogeneous. It has been suggested by several groups that it may be worthwhile to implement some cores that are specially tuned to execute common code patterns. One such common application that will execute on all future processors is of course the operating system. Many future workloads will spend a large fraction of their execution time within privileged mode, either executing system calls or pure operating system functionality. Vast transistor budgets and relatively low on-chip communication latencies make it feasible to off-load the execution of privileged instruction sequences on to such a custom core. In this paper, we first examine this off-load approach and attempt to understand its benefits. We then try to architect a solution that captures the benefits of off-loading and eliminates its disadvantages. In essence, the benefits of offloading can be attributed to reduced cache interference, while its disadvantages are the high latency costs for off-load and cache coherence. Our proposed solution employs a special OS cache per core and improves performance by up to 18% for OS-intensive workloads without any significant addition of transistors. We consider several design choices for this OS cache and argue that it is a better use of transistor and power budget than the off-loading approach when both adding to the transistor budget or leaving it unchanged

Hardware prediction of OS run-length for fine-grained resource customization

poste

A case for increased operating system support in chip multi-processors

Journal ArticleWe identify the operating system as one area where a novel architecture could significantly improve on current chip multi-processor designs, allowing increased performance and improved power efficiency. We first show that the operating system contributes a non-trivial overhead to even the most computationally intense workloads and that this OS contribution grows to a significant fraction of total instructions when executing interactive applications. We then show that architectural improvements have had little to no effect on the performance of the operating system over the last 15 years. Based on these observations we propose the need for increased operating system support in chip multiprocessors. Specifically we consider the potential of a separate Operating System Processor (OSP) operating concurrently with General Purpose Processors (GPP) in a Chip Multi-Processor (CMP) organization