Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis

Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data remanence. Thus, a sudden power shutdown may not delete data entirely, giving the opportunity to steal data. The biggest challenge for any technique aiming to secure the cache memory is performance penalty. Techniques based on data scrambling have demonstrated that security can be improved with a limited reduction in performance. However, they still cannot resist side-channel attacks like power or electromagnetic analysis. This paper presents a review of known attacks on memories and countermeasures proposed so far and an improved scrambling technique named random masking interleaved scrambling technique (RM-ISTe). This method is designed to protect the cache memory against cold-boot attacks, even if these are boosted by side-channel techniques like power or electromagnetic analysis.Postprint (author's final draft

On the use of error detecting and correcting codes to boost security in caches against side channel attacks

Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys. In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists against side channel attacks, in particular using power analysis. Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is selected to make the IST technique robust against side channel attacks using power analysis.Postprint (author’s final draft

Regional Specialisation and Economic Concentration in Romania

The purpose of the paper is to give an overview of the changes in the structure of industries in Romania, specifically on the questions (1) whether the industrial structures become more similar or more different in the Romanian regions and (2) whether the Romanian industries become more concentrated or more dispersed. EUROSTAT regional data on Gross Value Added and employed population for the period of 2000-2013 are used in order to calculate several statistical indices of specialization and concentration (Krugman, Entropy, Hirschman-Herfindahl, Lilien Index and Gini coefficient). By comparing the values of these different measurements, the main finding is that Romanian regions become less specialized, while industries become slightly more concentrated. The speed of structural changes in all Romanian regions registered a noticeable slowdown of the speed of sectoral changes after the economic crisis. Our conclusions provide useful information for the economic policy makers in investment funds allocation or employment measures designing

Defending cache memory against cold-boot attacks boosted by power or EM radiation analysis

Some algorithms running with compromised data select cache memory as a type of secure memory where data is confined and not transferred to main memory. However, cold-boot attacks that target cache memories exploit the data remanence. Thus, a sudden power shutdown may not delete data entirely, giving the opportunity to steal data. The biggest challenge for any technique aiming to secure the cache memory is performance penalty. Techniques based on data scrambling have demonstrated that security can be improved with a limited reduction in performance. However, they still cannot resist side-channel attacks like power or electromagnetic analysis. This paper presents a review of known attacks on memories and countermeasures proposed so far and an improved scrambling technique named random masking interleaved scrambling technique (RM-ISTe). This method is designed to protect the cache memory against cold-boot attacks, even if these are boosted by side-channel techniques like power or electromagnetic analysis

On the use of error detecting and correcting codes to boost security in caches against side channel attacks

Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys. In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists against side channel attacks, in particular using power analysis. Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is selected to make the IST technique robust against side channel attacks using power analysis

Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories

Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the stored data that uses interleaved scrambling vectors which reduce the power consumption if compared to the standard scrambling technique. Dissemination rules for the retained data in the cache are employed, in order to make data unusable if retrieved successfully by any type of attack. The proposed technique is analyzed and evaluated from several points of views, including area overhead, power consumption and time performance

Defeating simple power analysis attacks in cache memories

A wide range of attacks that target cache memories in secure systems have been reported in the last half decade. Cold-boot attacks can be thwarted through the recently proposed Interleaved Scrambling Technique (IST). However, side channel attacks like the Simple Power Analysis (SPA) can still circumvent this protection. Error detection and correction codes (EDC/ECC) are employed in memories to increase reliability, but they can also be used to increase the security. This paper proposes to boost the IST with an ECC code in order to create a cache resistant against SPA-attacks. The redundancy provided by the ECC code is used to create confusion by enlarging the search space where the hacker has to look for to find the secret keys

On the use of error detecting and correcting codes to boost security in caches against side channel attacks

Microprocessor memory is sensitive to cold boot attacks. In this kind of attacks, memory remanence is exploited to download its content after the microprocessor has been struck by a hard boot. If just in this moment, a crypto-algorithm was in execution, the memory data can be downloaded into a backup memory and specialized tools can be used to extract the secret keys. In the main memory data can be protected using efficient encryption techniques but in caches this is not possible unless the performance becomes seriously degraded. Recently, an interleaved scrambling technique (IST) was presented to improve the security of caches against cold boot attacks. While IST is effective for this particular kind of attacks, a weakness exists against side channel attacks, in particular using power analysis. Reliability of data in caches is warranted by means of error detecting and correcting codes. In this work it is shown how these kinds of codes can be used not only to improve reliability but also the security of data. In particular, a self-healing technique is selected to make the IST technique robust against side channel attacks using power analysis

Interleaved Scrambling Technique: A Novel Low-Power Security Layer for Cache Memories

Memory systems security has increased over the last decade due to the sensitive information which is stored in plain text. Device specific attacks, such as cold-boot and sidechannel monitoring have been reported as being successfully in retrieving encryption and private keys from algorithms like AES and RSA. In this paper, we propose a new technique of securing the cache memories by scrambling the stored data that uses interleaved scrambling vectors which reduce the power consumption if compared to the standard scrambling technique. Dissemination rules for the retained data in the cache are employed, in order to make data unusable if retrieved successfully by any type of attack. The proposed technique is analyzed and evaluated from several points of views, including area overhead, power consumption and time performance

Improving security in cache memory by power efficient scrambling technique

The last decade has recorded an increase in security protocols for integrated circuits and memory systems, because of device specific attacks such as side-channel monitoring and cold boot and also because sensitive information is stored in such devices. The scope of this study is to propose new security measures which can be applied in memory systems, in order to make the stored data unusable, if retrieved successfully by any type of attack. The security technique uses interleaved scrambling vectors to scramble the data retained in a memory system and employs several dissemination rules. The proposed technique is investigated and assessed from several perspectives, such as power consumption, time performance and area overhead