Albiglutide and cardiovascular outcomes in patients with type 2 diabetes and cardiovascular disease (Harmony Outcomes): a double-blind, randomised placebo-controlled trial

Background: Glucagon-like peptide 1 receptor agonists differ in chemical structure, duration of action, and in their effects on clinical outcomes. The cardiovascular effects of once-weekly albiglutide in type 2 diabetes are unknown. We aimed to determine the safety and efficacy of albiglutide in preventing cardiovascular death, myocardial infarction, or stroke. Methods: We did a double-blind, randomised, placebo-controlled trial in 610 sites across 28 countries. We randomly assigned patients aged 40 years and older with type 2 diabetes and cardiovascular disease (at a 1:1 ratio) to groups that either received a subcutaneous injection of albiglutide (30–50 mg, based on glycaemic response and tolerability) or of a matched volume of placebo once a week, in addition to their standard care. Investigators used an interactive voice or web response system to obtain treatment assignment, and patients and all study investigators were masked to their treatment allocation. We hypothesised that albiglutide would be non-inferior to placebo for the primary outcome of the first occurrence of cardiovascular death, myocardial infarction, or stroke, which was assessed in the intention-to-treat population. If non-inferiority was confirmed by an upper limit of the 95% CI for a hazard ratio of less than 1·30, closed testing for superiority was prespecified. This study is registered with ClinicalTrials.gov, number NCT02465515. Findings: Patients were screened between July 1, 2015, and Nov 24, 2016. 10 793 patients were screened and 9463 participants were enrolled and randomly assigned to groups: 4731 patients were assigned to receive albiglutide and 4732 patients to receive placebo. On Nov 8, 2017, it was determined that 611 primary endpoints and a median follow-up of at least 1·5 years had accrued, and participants returned for a final visit and discontinuation from study treatment; the last patient visit was on March 12, 2018. These 9463 patients, the intention-to-treat population, were evaluated for a median duration of 1·6 years and were assessed for the primary outcome. The primary composite outcome occurred in 338 (7%) of 4731 patients at an incidence rate of 4·6 events per 100 person-years in the albiglutide group and in 428 (9%) of 4732 patients at an incidence rate of 5·9 events per 100 person-years in the placebo group (hazard ratio 0·78, 95% CI 0·68–0·90), which indicated that albiglutide was superior to placebo (p<0·0001 for non-inferiority; p=0·0006 for superiority). The incidence of acute pancreatitis (ten patients in the albiglutide group and seven patients in the placebo group), pancreatic cancer (six patients in the albiglutide group and five patients in the placebo group), medullary thyroid carcinoma (zero patients in both groups), and other serious adverse events did not differ between the two groups. There were three (<1%) deaths in the placebo group that were assessed by investigators, who were masked to study drug assignment, to be treatment-related and two (<1%) deaths in the albiglutide group. Interpretation: In patients with type 2 diabetes and cardiovascular disease, albiglutide was superior to placebo with respect to major adverse cardiovascular events. Evidence-based glucagon-like peptide 1 receptor agonists should therefore be considered as part of a comprehensive strategy to reduce the risk of cardiovascular events in patients with type 2 diabetes. Funding: GlaxoSmithKline

Effect of Metal oxide semiconductor field-effect transistors threshold voltage variation on high-performance circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 95-101).The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, limit energy consumption, control power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. One such challenge is the expected increase in threshold voltage variation due to worsening short channel effect. This thesis will address three specific circuit design challenges arising from increased threshold voltage variation and present prospective solutions. First, with supply voltage scaling, control of die-to-die threshold voltage variation becomes critical for maintaining high yield. An analytical model will be developed for existing circuit technique that adaptively biases the body terminal of MOSFET devices to control this threshold voltage variation. Based on this model, recommendations on how to effectively use the technique in future technologies will be presented. Second, with threshold voltage scaling, sub-threshold leakage power is expected to be a significant portion of total power in future CMOS systems. Therefore, it becomes imperative to accurately predict and minimize leakage power of such systems, especially with increasing within-die threshold voltage variation. A model that predicts system leakage based on first principles will be presented and a circuit technique to reduce system leakage without reducing system performance will be discussed.(cont.) Finally, due to different processing steps and short channel effects, threshold voltage of devices of same or different polarities in the same neighborhood may not be matched. This will introduce mismatch in the device drive currents that will not be acceptable in some high performance circuits. In the last part of the thesis, voltage and current biasing schemes that minimize the impact of neighborhood threshold voltage mismatch will be introduced.by Siva G. Narendra.Ph.D

Low-voltage-swing Monolithic DC-DC Conversion

Abstract—A low-voltage-swing MOSFET gate drive technique is proposed in this paper for enhancing the efficiency characteristics of high-frequency-switching dc–dc converters. The parasitic power dissipation of a dc–dc converter is reduced by lowering the voltage swing of the power transistor gate drivers. A comprehensive circuit model of the parasitic impedances of a monolithic buck converter is presented. Closed-form expressions for the total power dissipation of a low-swing buck converter are proposed. The effect of reducing the MOSFET gate voltage swings is explored with the proposed circuit model. A range of design parameters is evaluated, permitting the development of a design space for full integration of active and passive devices of a low-swing buck converter on the same die, for a target CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is lower than a standard full voltage swing. An efficiency of 88 % at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 to 0.9 V with a low-swing dc–dc converter based on a 0.18- m CMOS technology. The power dissipation of a low-swing dc–dc converter is reduced by 27.9 % as compared to a standard full-swing dc–dc converter. Index Terms—Buck converter, dc–dc converters, enhanced efficiency, high frequency, low power, low swing, monolithic integration, on-chip voltage conversion, parameter optimization, parasitic impedances, power dissipation modeling, power supply, reduced energy dissipation, reduced voltage swing, switching voltage regulator. I

@ 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Cascode Monolithic DC-DC Converter for Reliable Operation at High Input Voltages

Abstract. A caseode bridge circuit for monolithic switching DC-DC converters operating at high input voltages is proposed in this paper. The proposed circuit can also be used as an I/O buffer to interface circuits operating at significantly different voltages. The circuit technique permits the full integration of the active and passive devices of a switching DC-DC converter with a high voltage conversion ratio in a standard low voltage CMOS technology. The cascode bridge structure guarantees the reliable operation of deep submicrometer MOSFETs without exposure to high voltage stress while operating at high input and output voltages. With the proposed circuit technique, steady-state voltage differences between the terminals of all of the MOSFETs in a switching DC-DC converter are maintained within a range imposed by a target low voltage CMOS technology. High-to-Iow DC-DC converters operating at input voltages up to three times as high as the maximum voltage that can be directly applied across the terminals of a MOSFET are described. An efficiency of 79.6 % is achieved for 5.4 volts to 0.9 volts conversion assuming a 0.18 /LmCMOS technology. The DC-DC converter operates at a switching frequency of 97 MHz while supplying a DC current of 250 mA to the load. Key Words: low voltage DC-DC converters, monolithic voltage regulators, low voltage CMOS technology, MOSFET reliability issues, high voltage stress 1

Monolithic DC-DC converter analysis and MOSFET gate voltage optimization

Abstract — The design of an efficient monolithic buck converter is presented in this paper. A low swing MOSFET gate drive technique is proposed that improves the efficiency characteristics of a DC-DC converter. A model of the parasitic impedances of a buck converter is developed. With this model, a design space is described which characterizes the integration of both active and passive devices of a buck converter onto the same die based on a 0.18 µm CMOS technology. The optimum gate voltage swing of a power MOSFET that maximizes efficiency is shown to be lower than a standard full voltage swing. An efficiency of 88 % at a switching frequency of 102 MHz is achieved for a voltage conversion from 1.8 volts to 0.9 volts with a low swing DC-DC converter. The power dissipation of a low swing DC-DC converter is reduced by 24.5%, improving the efficiency by 3.9 % as compared to a full swing DC-DC converter. losses of the off-chip power generation and distribution increase, further degrading the efficiency of DC-DC converters. Integrating both the active and passive devices of a buck converter onto the same die as a dual-VDD microprocessor has been proposed in [2] in order to improve efficiency, reduce fabrication costs, and decrease the number of I/O pads dedicated for power delivery on the microprocessor die. A model has been developed and an analysis is presented that describes a design space for full integration of active and passive devices onto the same die as a dual-VDD microprocessor [2]. Integrated active devices VDD1 P 1 External passive devices MOSFET gate drivers Filter inductor V DD2 1

Efficiency Analysis of a High Frequency Buck Converter for On-Chip Integration with a Dual-VDD

An analysis of the power characteristics of a buck converter is presented in this paper. A high switching frequency is the key design parameter that simultaneously permits monolithic integration and high efficiency. A parasitic model of the buck converter is developed. With this model, a design space is determined that allows integration of active and passive devices on the same die for a target technology. An efficiency of 88.4 % at a switching frequency of 477 MHz is demonstrated for a voltage conversion from 1.2 volts to 0.9 volts while supplying 9.5 amperes average current assuming an 80 nm CMOS technology. The area occupied by the buck converter is 12.6 mm 2. An analytic estimate of the efficiency is shown to be within 2.4 % of simulation at the target design point. Full integration of a high efficiency buck converter on the same die with a dual-VDD microprocessor is shown to be feasible. 1

Effective dielectric thickness scaling for high-K gate dielectric MOSFETs

It has been shown recently that the short channel performance worsens for high-K dielectric MOSFETs as the physical thickness to the channel length ratio increases, even when the effective oxide thickness (EOT) is kept identical to that of SiO2. In this work we have systematically evaluated the effective dielectric thickness for different Kgate to achieve targeted threshold voltage (Vt), drain-induced barrier lowering (DIBL) and Ion/Ioff ratio for different technology generations down to 50 nm using 2-Dimensional process and device simulations. Our results clearly show that the oxide thickness scaling for high-K gate dielectrics and SiO2 follow different trends and the fringing field effects must be taken into account for estimation of effective dielectric thickness when SiO2 is replaced by a high-K dielectric

Cascode buffer for monolithic voltage conversion operating at high input supply voltages

A high-to-low switching DC-DC converter that operates at input supply voltages up to two times as high as the maximum voltage permitted in a nanometer CMOS technology is proposed in this paper. The circuit technique is based on a cascode bridge that maintains the steady-state voltage differences among the terminals of all of the transistors within a range imposed by a specific fabrication technology. The proposed circuit technique permits the full integration of active and passive devices of a switching DC-DC converter with a high voltage conversion ratio in a standard low voltage CMOS process. An efficiency of 87.8 % is achieved for 3.6 volts to 0.9 volts conversion assumin