Silicon Photodiodes for Low Penetration Depth Beams such as DUV/VUV/EUV Light and Low-Energy Electrons

Delft Institute of Microsystems and Nanoelectronics (DIMES)Applied Science

High-performance bifet process for analog integrated circuits

Electrical Engineering, Mathematics and Computer Scienc

Large-area selective CVD epitaxial growth of Ge on Si substrates

Selective epitaxial growth of crystalline Ge on Si in a standard ASM Epsilon 2000 CVD reactor is investigated for the fabrication of Ge p+n diodes. At the deposition temperature of 700?C, most of the lattice mismatch-defects are trapped within first 300nm of Ge growth and good quality single crystal Ge is achieved within a layer thickness of approximately 1 ?m on window sizes up to hundreds of ?m2. For p+n junction fabrication, a sequence of pure-Ga and then pure-B depositions are utilized for the ultrashallow p-doping of As-doped Ge-islands. The I-V characterization of the diodes confirms the good quality of the Ge and ideality factors of ~ 1.1 with low saturation currents are reliably achievedDIMESElectrical Engineering, Mathematics and Computer Scienc

Analytical model of I–V characteristics of arbitrarily shallow p-n junctions

For the first time, an analytical model of arbitrarily shallow p-n junctions is presented. Depending on the junction depth, electrical characteristics of ultrashallow p-n junctions can vary from the characteristics of standard Schottky diodes to standard deep p-n junctions. This model successfully unifies the standard Schottky and p-n diode expressions. In the crossover region, where the shallow doping region can be totally depleted, electrical characteristics phenomenologically substantially different from typical diode characteristics are predicted. These predictions and the accuracy of the presented model are evaluated by comparison with the MEDICI simulations. Furthermore, ultrashallow n+-p diodes were fabricated, and the anomalous behavior in the crossover regime was experimentally observed.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc

Electrothermal limitations on the current density of high-frequency bipolar transistors

Electrical Engineering, Mathematics and Computer Scienc

Material-Inversion Solid-Phase Epitaxy of p+ Si forElevated Junctions

MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

Crystallographic Silicon-Etching for Ultra-High Aspect-Ratio FinFET

MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

CVD Delta-Doped Boron Surface Layers for Ultra-Shallow Junction Formation

MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc

Insights to emitter saturation current densities of boron implanted samples based on defects simulations

Emitter saturation current densities, Joe have been investigated with different boron implantation dose and annealing conditions. The higher thermal budgets used here are shown experimentally to improve Joe, implying more complete defect dissolution. Simulations show that significant degradation in Joe can be attributed to the presence of dislocation loops. In addition, in cases where dislocation loops have been annealed, high dose boron implantation still results in stable boron interstitial clusters, which contributes to Joe degradation.MicroelectronicsElectrical Engineering, Mathematics and Computer Scienc