A Scheduling Method for Asynchronous VLSI System Design

Introduction With the revival of interest in asynchronous systems there is a need for methods and tools for the high-level synthesis tailored for them. Although there are various methodologies already published that deal with synchronous design, there is not much work developed for the scheduling of asynchronous VLSI systems. In particular, we are interested in a methodology to schedule asynchronous pipelines. In this note we propose a method for scheduling asynchronous VLSI systems, and then show how this method, together with existing synchronous methodologies can be used to synthesize asynchronous pipelines. 2 Asynchronous scheduling Given a data flow graph (DFG), a set of constraints (performance/area), and a set of libraries of functional modules, the task of scheduling an asynchronous system is to decide how to place the functional modules so that they satisfy the constraints, and at the same time trying to minimize the necessary resources. In the meth