Patterned accumulation mode capacitive phase shifter

A semiconductor waveguide device includes a first semiconductor layer having a first surface, wherein the first surface comprises a first protrusion and a second protrusion collectively forming a first trench in the first semiconductor layer, a second semiconductor layer having a second surface opposing the first surface of the first semiconductor layer, and an insulator layer disposed between and in contact with the first surface and the second surface, wherein the first semiconductor layer, the second semiconductor layer, and the insulator layer form a semiconductor waveguide region, and wherein the first trench is configured to confine a mode of light beam propagation in the semiconductor waveguide regio

Patterned accumulation mode capacitive phase shifter

A semiconductor waveguide device includes a first semiconductor layer having a first surface, wherein the first surface comprises a first protrusion and a second protrusion collectively forming a first trench in the first semiconductor layer, a second semiconductor layer having a second surface opposing the first surface of the first semiconductor layer, and an insulator layer disposed between and in contact with the first surface and the second surface, wherein the first semiconductor layer, the second semiconductor layer, and the insulator layer form a semiconductor waveguide region, and wherein the first trench is configured to confine a mode of light beam propagation in the semiconductor waveguide regio

Parametric fault simulation and test vector generation

Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach extended by hard fault testing has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx

Testing of Embedded A/D converters in MixedSignal Circuit

In this paper, a complete functional testing of embedded ADC is pre-sented. The integral non-linearity error, INLE, differential non-linearity error, DNLE, offset error, OSE, gain error and the signal-to-noise ratio, SNR are tested. The problem related to the propagation of the analog sig-nal to the input of the ADC and the observation of the digital output of the converter at the output of the digital circuit are discussed. The two means for functional testing are discussed: the histogram and he FFT. To observe the outputs of the ADC at the digital circuit, the inverse function of the digital circuit is computed. This can be done by inverting the transfer function of the digital circuit whenever it is available. In the other case, when the digital circuit structure is available, the inverse of the digital cir-cuit is found by boolean function manipulation. In order to present a complete test for an ADC embedded in a mixed-signal circuit, some performances have to be measured at the output of the mixed-signal circuit. These performances are: the integral non-linearit