Bus Encoding for Low-Power High-Performance Memory Systems

High-performance memory buses consume large energy as they include termination networks, BiCMOS and/or open-drain output. This paper introduces power reduction techniques for memory systems deliberating on burst-mode transfers over the high-speed bus specifications such as Low Voltage BiCMOS (LVT), Gunning Transfer Logic (GTL+) and Stub Series Termination Logic (SSTL 2) which are widely used. The reduction techniques take both the static and the dynamic power consumption into account because most high-performance bus drivers and end-termination networks dissipate significant static power as well. Extensive performance analysis is conducted through mathematical analysis and trace datadriven simulations. We had reduction of 14% with random data and up to 67.5% with trace data