Parallel algorithm for analysis of high-speed interconnects

In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for this class of simulations to be performed efficiently. The proposed method exploits the recently developed algorithm using transverse partitioning and waveform relaxation. A new partitioning algorithm is also proposed to create additional parallelism during transient simulations. In this approach, for a simulation of m lines run on p processors, the computational complexity is 0(mp-1). This provides considerable savings as opposed to O(m β),3 ≤ ,β ≤ 4 for full coupled-line simulations

Efficient parallel scheduler for circuit simulation exploiting binary link formulations

As circuit sizes increase, a means to improve the performance of simulations is constantly demanded, without sacrificing the accuracy of the results. To achieve this goal, a new parallel scheduler is presented exploiting binary link formulations that allows modern multi-core processors to achieve superior performance. These improvements are obtained without sacrificing accuracy or resorting to iterative techniques

Coupled high-speed interconnect analysis on parallel platforms

Signal integrity analysis is becoming extremely important in validation of high-speed designs. In a system containing highspeed interconnects, the presence of a large number of coupled lines presents difficult challenges for performing fast simulations. In this paper, a novel parallel algorithm based on both physical and time-domain partitioning is proposed that allows for the efficient analysis of circuits containing large number of coupled lines. The proposed method exploits the recently developed method of combining transverse partitioning and wavefonn relaxation. Examples are provided to demonstrate the efficiency and scalability of the proposed algorithm

Addressing partitioning issues in parallel circuit simulation

With the rapidly increasing demands for high-speed and high-density electronic products, complexity and size of the associated circuits have increased significantly in the recent years. The large size of these circuits poses major challenges for simulation in terms of excessive CPU cost. To address this, a parallel circuit simulation algorithm has been recently developed that allows modern multicore processors to be exploited to realize higher parallel scalability with an increasing number of CPUs. In this paper, several methods have been proposed to improve efficiency and flexibility during the partitioning of analog circuits. The proposed methods reduce the constraints for partitioning, allowing a more efficient set of partitions to be found, which improves scalability when used in a parallel implementation

Parallel simulation of massively coupled interconnect networks

In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for simulations of massively coupled interconnects to be performed efficiently. New methods based on physical and time-domain partitioning are developed to create parallelism during transient simulations of large coupled interconnects. In addition, the proposed method exploits the recently developed waveform relaxation techniques to decouple and parallelize the large coupled simulation problem. In this approach, for a simulation of nL lines run on n P processors, the computational complexity is O(nLn P -1). This provides considerable savings as opposed to ≤ β ≤ 4 for full coupled-line simulations

DEPACT: Delay extraction-based passive compact transmission-line macromodeling algorithm

With the continually increasing operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, several algorithms were proposed for macromodeling and transient analysis of distributed transmission line interconnect networks. The techniques such as method-of-characteristics (MoC) yield fast transient results for long delay lines. However, they do not guarantee the passivity of the macromodel. It has been demonstrated that preserving passivity of the macromodel is essential to guarantee a stable global transient simulation. On the other hand, methods such as matrix rational approximation (MRA) provide efficient macromodels for lossy coupled lines, while preserving the passivity. However, for long lossy delay lines this may require higher order approximations, making the macromodel inefficient. To address the above difficulties, this paper presents a new algorithm for passive and compact macromodeling of distributed transmission lines. The proposed method employs delay extraction prior to approximating the exponential stamp to generate compact macromodels, while ensuring the passivity. Validity and efficiency of the proposed algorithm is demonstrated using several benchmark examples

Delay-extraction-based sensitivity analysis of multiconductor transmission lines with nonlinear terminations

An efficient approach is presented for time-domain sensitivity analysis of lossy multiconductor transmission lines with respect to electrical and/or physical parameters. The proposed method employs delay extraction prior to approximating the matrix exponential stamp of the line and guarantees macromodel passivity. A delay-extraction-based equivalent circuit for sensitivity analysis is derived in a closed form, leading to significant computational advantages