3D Stacking: A New Era for the Integrated Circuit

Muhannad Bakir from the Nanotechnology Research Center at the Georgia Institute of Technology, presented a lecture at the Nano@Tech Meeting on March 30, 2010 at 12 noon in room 1116 of the Marcus Nanotechnology Building.Runtime: 60:29 minutesThe information revolution has been the most important economic event of the past century and its most powerful driver has been the silicon integrated circuit (IC). Over the past fifty years, the migration from BJT to CMOS technology combined with transistor scaling has produced exponential benefits in microchip productivity and performance. However, as silicon technology progresses beyond the 45 nm node, the performance of a system-on-a-chip (SoC) has lagged by progressively greater margins to reach the intrinsic limits of each particular generation of technology. A root cause of this lag is the fact that the capabilities of monolithic silicon technology per se have vastly surpassed those of the ancillary or supporting technologies that are essential to the full exploitation of a high performance SoC, especially in areas of cooling, off-chip signaling, and power delivery. The need for ever greater off-chip bandwidth will be especially problematic as the number of cores on a microprocessor increases. Revolutionary "silicon ancillary technologies" are needed to address these challenges. Of course, innovation in silicon ancillary technologies will have to be done in parallel with continued innovations at the chip level (improved scaled transistors and interconnects) as well as system architecture among other things. Three-dimensional (3D) system integration can be used to greatly enhance communication between ICs (larger bandwidth, lower latency, and lower energy per bit) as well as enable heterogeneous integration of technologies. However, 3D IC technology also presents challenges. Aside from issues relating to manufacturing, power delivery and cooling of a stack of logic chips presents many challenges. Simply put, it is difficult enough to cool and deliver power to a single processor today. Stacking multiple processors and memory chips, for example, presents formidable challenges that require advanced silicon ancillary technologies. These issues will be discussed in the seminar. This presentation will also discuss the unique opportunities and technologies for 3D heterogeneous integration of CMOS electronics with chemical and bio-sensors

Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration

Ph.D.Committee Chair: James D. Meind

Interconnects, System Integration, and Packaging of Electronics

Presented on August 21, 2014 at 12:00 p.m. in the Marcus Nanotechnology Building Conference Room 1116.Muhannad S. Bakir received his B.E.E. degree (Summa Cum Laude) from Auburn University, Auburn, AL, in 1999 and his M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology in 2000 and 2003, respectively. Bakir is currently an Associate Professor and the ON Semiconductor Junior Professor in the School of Electrical and Computer Engineering at Georgia Tech. His areas of interest include three-dimensional (3D) electronic system integration, advanced cooling and power delivery for 3D systems, heterogeneous system interconnection, biosensors and their integration with CMOS circuitry, and nanofabrication technology.Runtime: 63:41 minutesThis presentation will provide a retrospect and prospects for electronics interconnects, system integration, and packaging

Integrated interconnect technologies for 3D nanoelectronic systems

This cutting-edge book on off-chip technologies puts the hottest breakthroughs in high-density compliant electrical interconnects, nanophotonics, and microfluidics at your fingertips, integrating the full range of mathematics, physics, and technology issues together in a single comprehensive source

IPACK2005-73302 PROBE MODULE FOR WAFER-LEVEL TESTING OF GIGASCALE CHIPS WITH ELECTRICAL AND OPTICAL I/O INTERCONNECTS

ABSTRACT The bandwidth provided by optical interconnects makes them an attractive solution for chip-to-package and chip-to-chip communications. In such systems, chips will have optical I/O interconnects fabricated alongside their conventional electrical counterparts. Virtually no work has been previously reported relating to the testing of such chips at the wafer-level. The requirements for probe hardware needed to achieve this are identified, and probe module configurations based on these requirements are presented. A high-density micro-opto-electro-mechanicalsystems(MOEMS)-based probe substrate prototype for interfacing with chips having electrical and optical polymer pillar-base

Handbook of 3D integration: Volume 4: Design, test, and thermal management

This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration