2D Modelling of Mechanical Stress Evolution and Electromigration in Confined Aluminium Interconnects

A complete description for mechanical stress evolution and electromigration in confined Al interconnects, taking into account the microstructure features, is presented in this paper. In the last years there were proposed several 1D models for the time-dependent evolution of the mechanical stress in Al interconnect lines, since the time to failure of the line can be related to the time a critical value of the stress is reached. The present paper extends and improves the existing models in 2D using a two dimensional simulator based on finite element method. Also, the model makes an attempt to relate the stress/vacancy concentration evolution with the early resistance change of the Al lin

Integrated cascade of photovoltaic cells as a power supply for integrated circuits

ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard bipolar processes. Deep ion implantations have been used here to realize the multiple-junction structure. Power losses due to photocurrents originating from insulation junctions in the cascade can be kept to a minimum. The surface areas of two adjacent cells have to satisfy a definite relation to ensure the build-up of output voltage. Operating under sunlight conditions, 0.6 mW/cm2 has been generated in a cascade of three cells. With appropriate optical coatings on the silicon surface and optimized cell dimensions, it should be possible to generate a few milliwatts per cm2. The structures may have applications in electronic circuits for glass fibres or can be used to power small CMOS circuits

Early resistance change and stress/electromigrationmodeling in aluminium interconnects

A complete description for early resistance change and two dimensional simulation of mechanical stress evolution in confined Al interconnects, related to the electromigration, is given in this paper. The model, combines the stress/ vacancy concentration evolution with the early resistance change of the Al line, that could be [1] a fast technique for prediction of the MTF of a line compared to the conventional (accelerated) tests

Study of dynamics of charge trapping in a-Si:H/SiN TFTs

In this paper we present the study of the failure mechanism responsible for long-term degradation that ultimately leads to instability in a-Si:H/SiN TFTs. The experimental data points we obtain by monitoring in-situ the drain current during gate bias stress (forward and reverse bias) and relaxation could not be fitted with the models existent in the literature. A new model that we have christened "Progressive Degradation Model" (PDM) emerged. The model makes use of Heimann-Warfield theory of trapping/detrapping front. PDM achieves a consistent fit to any bias condition showing that the degradation can be modelled quantitatively yielding the number of traps involved, their position and the charge dispersion coefficient. According to PDM the degradation of electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites in a-SiN:H transitional region

Rise-time effects in ggnMOSt under TLP stress

In this paper the main mechanisms that lead the turn on of the parasitic bipolar transistor of a grounded gate nMOS transistor (ggnMOS) under TLP stress have been analyzed in detail in the sub-nanoseconds range by means of a mixed-mode simulator. We showed that the breakdown voltage of the ggnMOS measured in static conditions would underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise-time of the applied puls

Self-Evaluation Applied Mathematics 2003-2008 University of Twente

This report contains the self-study for the research assessment of the Department of Applied Mathematics (AM) of the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) at the University of Twente (UT). The report provides the information for the Research Assessment Committee for Applied Mathematics, dealing with mathematical sciences at the three universities of technology in the Netherlands. It describes the state of affairs pertaining to the period 1 January 2003 to 31 December 2008

Physics of electro-thermal effects in ESD protection devices

Damage in ESD protection devices can be caused by high local temperatures resulting from heat generation by an ESD pulse. In order to obtain physical insight into the process that leads to permanent damage, device simulations of coupled thermal and electrical behaviour have been performed. Additional to the potential and the electron and hole concentrations the lattice temperature is solved as a variable. Simulations of ESD pulses (forward bias) applied to a diode have been performed. The discharge mechanism could be visualised by using the coupled thermal/electrical model. Locations with considerable temperature rise that eventually lead to damage can be extracted from the calculated temperature distributions. Protection devices with optimum electrical and thermal characteristics can be designed by adjusting doping profiles and layout parameters. The buried layer of the protection device does not contribute in conducting current at high current levels. Therefore the buried layer is not functional in diodes that are subjected to ESD in forward bias. Measurements determining the ESD vulnerability of protection devices with and without buried layer confirm this fact

Turn-on speed of grounded gate NMOS ESD protection transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model

Vector representation of resonators in eigencoupling state space and eigenloss state space of piezoelectric ceramics

The calculation of the vector representation of resonators in the coupling and loss eigenstate spaces is presented. The coupling and loss eigenstates are located in a Cartesian coordinate system, together with the vector representation of resonators. The convenience of this representation is illustrated by calculations of the coupling factor and the loss factor in an octant of space in which resonators are positioned