A case study of a microsystems MSc curriculum

This paper tries to define the contents of master's programmes in Nanotechnology or Nanoengineering. This emerging technology holds large promises for industrial innovation and we need to prepare graduates properly as they will be confronted for most of their future careers with these new developments. The nano-world is a multidisciplinary world and the shortest way to a bad curriculum is filling it with a conglomerate of subjects from all disciplines. We should look for a philosophy and try to integrate disciplinary knowledge. Some of these questions are discussed and an implementation for a master's programme under the umbrella of Electrical Engineering is presented

2D Modelling of Mechanical Stress Evolution and Electromigration in Confined Aluminium Interconnects

A complete description for mechanical stress evolution and electromigration in confined Al interconnects, taking into account the microstructure features, is presented in this paper. In the last years there were proposed several 1D models for the time-dependent evolution of the mechanical stress in Al interconnect lines, since the time to failure of the line can be related to the time a critical value of the stress is reached. The present paper extends and improves the existing models in 2D using a two dimensional simulator based on finite element method. Also, the model makes an attempt to relate the stress/vacancy concentration evolution with the early resistance change of the Al lin

Early resistance change and stress/electromigrationmodeling in aluminium interconnects

A complete description for early resistance change and two dimensional simulation of mechanical stress evolution in confined Al interconnects, related to the electromigration, is given in this paper. The model, combines the stress/ vacancy concentration evolution with the early resistance change of the Al line, that could be [1] a fast technique for prediction of the MTF of a line compared to the conventional (accelerated) tests

Study of dynamics of charge trapping in a-Si:H/SiN TFTs

In this paper we present the study of the failure mechanism responsible for long-term degradation that ultimately leads to instability in a-Si:H/SiN TFTs. The experimental data points we obtain by monitoring in-situ the drain current during gate bias stress (forward and reverse bias) and relaxation could not be fitted with the models existent in the literature. A new model that we have christened "Progressive Degradation Model" (PDM) emerged. The model makes use of Heimann-Warfield theory of trapping/detrapping front. PDM achieves a consistent fit to any bias condition showing that the degradation can be modelled quantitatively yielding the number of traps involved, their position and the charge dispersion coefficient. According to PDM the degradation of electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites in a-SiN:H transitional region

Rise-time effects in ggnMOSt under TLP stress

In this paper the main mechanisms that lead the turn on of the parasitic bipolar transistor of a grounded gate nMOS transistor (ggnMOS) under TLP stress have been analyzed in detail in the sub-nanoseconds range by means of a mixed-mode simulator. We showed that the breakdown voltage of the ggnMOS measured in static conditions would underestimate the maximum voltage across the protection structure obtained by TLP stress, depending on the rise-time of the applied puls

Self-Evaluation Applied Mathematics 2003-2008 University of Twente

This report contains the self-study for the research assessment of the Department of Applied Mathematics (AM) of the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS) at the University of Twente (UT). The report provides the information for the Research Assessment Committee for Applied Mathematics, dealing with mathematical sciences at the three universities of technology in the Netherlands. It describes the state of affairs pertaining to the period 1 January 2003 to 31 December 2008

Turn-on speed of grounded gate NMOS ESD protection transistors

The turn-on speed of nMOS transistors (nMOST) is of paramount importance for robust Charged Device Model (CDM) protection circuitry. In this paper the nMOST turn-on time has been measured for the first time in the sub-halve nanosecond range with a commercial e-beam tester. The method may be used to improve CDM-ESD hardness by investigating the CDM pulse responses within circuit. Furthermore it is shown that the CDM results of various protection layouts can be simulated with a SPICE model