Evaluation of Material Profiles for III-V Nanowire Photodetectors

In this paper we report the simulation-based design of experiment (DoE) study for three different types of III-V based pin photodetectors operating at various wavelengths. Our DoE work shows that the optimal configuration for each device is strongly determined by the wavelength at which we are aiming to operate the photodetector and that a trade-off exists between low dark current and high photocurrent. Heterostructure devices provide the optimum performance in particular for longer wavelengths

Abrupt current switching due to impact ionization effects in Omega-MOSFET on low doped bulk silicon

In this paper, we report very abrupt current switching and hysteresis effects due to saddle point and impact ionization in low doped n-channel Omega-Gate MOSFET (Omega-MOSFET). The Omega-MOSFETs are fabricated on low-doped (8x10(14)cm(-3)) bulk silicon by bulk silicon isotropic etching and sacrificial oxidation. A specific abrupt impact ionization and hysteresis of I-D(V-DS) are observed at high drain voltage (V-DS > 11V) on transistors that have short channel effects (L=0.9-10um). This is explained by the accumulation of a hole pocket under the gate due to the formation of a saddle point region. An outstanding feature is that this effect can be exploited to abruptly switch from low to high current (2 decades of current) states of I-D(V-GS) characteristics with ultra-abrupt slopes of 5 to 10mV/dec. Moreover, the hysteresis window Delta V-GS similar to 500mV is suitable for DRAM memory. Dynamic switching characteristics and a retention time of up to tens of seconds are originally demonstrated. The proposed Omega-MOSFET stands as a very promising alternative to I-MOS devices, being more scalable and integrable on a standard (low cost) bulk-Si Multi-Gate FET platform. Its experimental performances are promising for both small-slope switches and dynamic RAM memories

Tunneling and Occupancy Probabilities: How Do They Affect Tunnel-FET Behavior?

In this letter, the occupancy and tunneling probabilities of interband tunneling devices are studied, pointing out the fundamental function of the source Fermi-Dirac distribution. Particularly, the reason for the degraded subthreshold swing, which is typical of devices with highly doped source, is explained, and its relation with the high-energy source Fermi tail is carefully analyzed. Simultaneously, the poor driving capability of Tunnel-FET devices is investigated, highlighting the primary role played by the occupancy functions

Small slope micro/nano-electronic switches

This paper discusses three categories of small slope electronic switches: the Tunnel FET the IMOS and the NEM-FET which are expected to bring added value compared to CMOS by presenting an abrupt subthreshold slope, smaller than the physical limit, 60mV/decade, of the solid-state MOS transistor at room temperature. Recent results and future promises are reported

In-Plane Monolithic Integration of Scaled III-V Photonic Devices

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits

Time-Delay Encoded Image Recognition in a Network of Resistively Coupled VO2 on Si Oscillators

Oscillatory neural networks based on insulator to metal transition of VO2 switches are implemented for image recognition. The VO2 oscillators are fabricated on silicon in a CMOS compatible process.A fullyconnected network of coupled oscillators is investigated using programmable resistors as coupling elements. In this approach, input of the image information and data processing is performed in the time domain. In particular, tuning the coupling resistors allows to control the phaserelationbetween the oscillators. This is used to memorize and recognize patterns in an analog circuit. The concept is demonstrated experimentally on a three-VO2 oscillator network, whereas simulations are performed on a larger 9-oscillators circuit