Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip

A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces. We show, for a range of NoC designs, that buffer sizes are determined with a run time comparable to existing analytical methods, and results comparable to exhaustive simulation

Evaluation of the throughput computed with a dataflow model -- A case study

Providing real-time guarantees in complex, heterogeneous, and embedded multiprocessor systems is an important issue because they affect the perceived quality. Digital signal processing algorithms are often modeled with dataflow models. A guaranteed minimum throughput can be computed from such dataflow model. In this paper we analyze three causes for the difference between the computed and measured throughput. We measure the throughput with a cycle accurate simulation. For our channel equalizer application the measured throughput is 10.1% higher than the computed minimum throughput

A multi-core architecture for in-car digital entertainment

Abstract—This paper presents a new multi-core architecture for in-car digital entertainment. Target functions vary from terrestrial reception, digital reception, and compressed audio, up to handsfree voice with acoustic echo cancellation and USB media playback, possibly in different user modes like single versus dual media sound. In the near future, new functions like near field communication, wireless streaming, storage, digital rights management, navigation and video become important. The main challenge is that the platform must be open for future functions, which are unknown at design time. Another challenge is to reduce the design effort by maximizing reuse of hardware and software, especially from related domains like Consumer Electronics (CE). This paper describes an multi-core architecture using a networkon-chip, which provides the required flexibility and scalability. The area overhead, due to the network, is estimated to be 1.5 % compared to the current architecture. Furthermore, it is shown that the latency is comparable to the current architecture. Categories and Subject Descriptors — System on Chip: Multi-core architecture and the use of this in car entertainment environment. Keywords—Embedded systems, multi-processor, networkon-chip, car radio, car entertainment, low cost. I