Area-selective atomic layer deposition on 2D monolayer lateral superlattices

Abstract The advanced patterning process is the basis of integration technology to realize the development of next-generation high-speed, low-power consumption devices. Recently, area-selective atomic layer deposition (AS-ALD), which allows the direct deposition of target materials on the desired area using a deposition barrier, has emerged as an alternative patterning process. However, the AS-ALD process remains challenging to use for the improvement of patterning resolution and selectivity. In this study, we report a superlattice-based AS-ALD (SAS-ALD) process using a two-dimensional (2D) MoS2-MoSe2 lateral superlattice as a pre-defining template. We achieved a minimum half pitch size of a sub-10 nm scale for the resulting AS-ALD on the 2D superlattice template by controlling the duration time of chemical vapor deposition (CVD) precursors. SAS-ALD introduces a mechanism that enables selectivity through the adsorption and diffusion processes of ALD precursors, distinctly different from conventional AS-ALD method. This technique facilitates selective deposition even on small pattern sizes and is compatible with the use of highly reactive precursors like trimethyl aluminum. Moreover, it allows for the selective deposition of a variety of materials, including Al2O3, HfO2, Ru, Te, and Sb2Se3

Large Memory Window of van der Waals Heterostructure Devices Based on MOCVD-Grown 2D Layered Ge4Se9

Van der Waals (vdW) heterostructures have drawn much interest over the last decade owing to their absence of dangling bonds and their intriguing low-dimensional properties. The emergence of 2D materials has enabled the achievement of significant progress in both the discovery of physical phenomena and the realization of superior devices. In this work, the group IV metal chalcogenide 2D-layered Ge4Se9 is introduced as a new selection of insulating vdW material. 2D-layered Ge4Se9 is synthesized with a rectangular shape using the metalcorganic chemical vapor deposition system using a liquid germanium precursor at 240 degrees C. By stacking the Ge4Se9 and MoS2, vdW heterostructure devices are fabricated with a giant memory window of 129 V by sweeping back gate range of +/- 80 V. The gate-independent decay time reveals that the large hysteresis is induced by the interfacial charge transfer, which originates from the low band offset. Moreover, repeatable conductance changes are observed over the 2250 pulses with low non-linearity values of 0.26 and 0.95 for potentiation and depression curves, respectively. The energy consumption of the MoS2/Ge4Se9 device is about 15 fJ for operating energy and the learning accuracy of image classification reaches 88.3%, which further proves the great potential of artificial synapses