Using rewriting techniques to produce code generators and proving them correct

AbstractA major problem in deriving a compiler from a formal definition is the production of correct and efficient object code. In this context, we propose a solution to the problem of code-generator generation.Our approach is based on a target machine description where the basic concepts used (storage classes, access modes, access classes and instructions) are hierarchically described by tree patterns. These tree patterns are terms of an abstract data type. The program intermediate representation (input to the code generator) is a term of the same abstract data type.The code generation process is based on access modes and instruction template-driven rewritings. The result is that each program instruction is reduced to a sequence of elementary machine instructions, each of them representing an instance of an instruction template.The axioms of the abstract data type are used to prove that the rewritings preserve the semantics of the intermediate representation

Automatic generation of schedulers in the framework of the PAGODE system

Projet CHLOEPagode is a back-end generator which produces automatically the various engines of a code generator (instruction selector, scheduler and register allocator) from a target machine specification. This report mainly focuses on the features of the target machine which aim at producing the scheduler, and on the heuristics used by the kernel of the scheduler

Using clp(FD) to Support Instruction Schedulers for Multi-issue Pipelined Architectures

Projet DIRROCQIn the conventional models of pipelined architectures, pipeline conflicts are generally avoided through techniques like reservation tables. They are intended to describe the run time of instructions for which the delays between the execution stage and the fetch one is a constant depending only on the instruction. In fact actual superscalar processors don't comply this model since such delays are context dependent. The proposed approach fully supports slackness in the run time flow of execution. We advocate a model that is based on the concurrency of tasks performed by pipelines rather than the concurrent usage of resources as most current approaches do. The scheduling algorithm is based on the properties of this model. Since most of the constraints can be stated as linear equations or inequations, an implementation using CLP with finite domains is straightforward

Rapports de Recherche

Pagode is a back-end generator that produces automatically the various engines of a code generator (instruction selector, scheduler and register allocator) from a target machine specification. This technical report presents the system in its first release and makes up a user's guide. Keywords: instruction selection, register allocation, pipeline, code scheduling R'esum'e Pagode est un constructeur de g'en'erateurs de code qui produit les diff'erents moteurs (s'electeur d'instructions, module d'ordonnancement de code et allocateur de registres) d'un g'en'erateur de code de facon modulaire. Ce rapport technique pr'esente la premi`ere version de ce syst`eme et constitue un manuel d'utilisation. Mots-Cl'es : g'en'eration de code, allocation de registres, ordonnancement de code Contents 0.1 Introduction : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 1 The Scala language 10 1.1 Introduction : : : : : : : : : : : : : : : : : : : : : : : : : : : : ..

IRs and their specification in the PAGODE back-end generator

In this paper, we present an approach to handle the automatic generation of back-ends from a completely declarative specification of the target machine that does not require any knowledge of the code generation process. This paper mainly focuses on the various levels of intermediate representations used in a back-end based on the Pagode system. This approach has been validated by the production of a C-SPARC compiler. 1 Introduction High level languages and machine languages have different computation models. The compilation process can be split into several translation phases. Usually, a front-end translates the source program into an intermediate representation, the middle part works on the semantics and rearranges computations, translating to a lower level IR, and finally the back-end translates the last IR to actual target machine code. A back-end must not only map data access paths to hardware addressing modes, choose target machine instructions for IR code and allocate registers,..

PAGODE: a realistic back-end generator

Pagode is an advanced back-end generator that produces automatically a code generator from a specification of the processor. Such a specification is easy to derive from the various documents provided by the processor manufacturer, without requiring any additional code-generation expertise. This paper mainly focuses on the generic aspects of the Pagode system which is open enough to integrate the most powerful algorithms corresponding to the various subtasks of the code generation process. This approach has been validated by the production of a C-SPARC compiler in the framework of an industrial technology. Contents 1 Introduction 2 2 A generic back-end 3 3 Generic engines using the processor specification 4 3.1 The processor specification : : : : : : : : : : : : : : : : : : : : : : : : : : : : 4 3.2 A generic instruction selector : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.3 A short example : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 3.4 The gen..

Using clp (FD) to support instruction schedulers for multi-issue pipelined architectures

Theme 2 - Genie logiciel et calcul symbolique - Projet dirrocqSIGLEAvailable at INIST (FR), Document Supply Service, under shelf-number : 14802 E, issue : a.1996 n.3078 / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Automatic generation of schedulers in the framework of the PAGODE system

SIGLEAvailable at INIST (FR), Document Supply Service, under shelf-number : 14802 E, issue : a.1993 n.1950 / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc

Meta-generation de code par reecriture de termes guidee par modeles d'arbres

SIGLECNRS 14802 E / INIST-CNRS - Institut de l'Information Scientifique et TechniqueFRFranc