High-voltage pulse generator based on sequentially charged MMC-SMs operating in a voltage-boost mode

Pulse forming networks and Marx generators are the classical rectangular waveform pulse generators (PGs). They are inflexible and their capacitors must be fully charged to the required voltage from 0V before delivering each high-voltage (HV) pulse. They are only able to generate unipolar pulses; if bipolar pulses are sought another generator fed from a negative supply voltage is added. Recently, several power electronics based PGs have been proposed. This paper presents an HV power electronics based PG, which is based on Half-Bridge Modular Multilevel Converter (HB-MMC) sub-modules (SMs) charged sequentially in a voltage boost mode. Each SM capacitor and main switch form a boost converter with the charging input supply and inductor. As a result, all SM capacitors are charged to a voltage greater than the input. During the discharging process the SM capacitors are connected in series, producing a rectangular HV pulse across the load. The proposed charging method allows a reduction in the converter footprint in comparison with recently proposed MMC sequentially charged PG topologies. Although only rectangular pulse waveforms are sought in this paper, a SM capacitor voltage balance method allows multilevel pulse generation. The viability of the proposed converter is confirmed by MATLAB/Simulink simulation and scaled-down experimentation

Evaluation of drain-source voltage in switch transient time intervals as gate oxide degradation precursor of SiC power MOSFETs

Gate oxide degradation is a major chip-related reliability issue in Silicon Carbide power MOSFETs. Being focused on turn-on/-off transient behavior of the switch, drain-source voltage waveform is employed as a gate oxide degradation precursor in this paper. Precursor evaluation is carried out in various operating conditions of the switch

Gate oxide degradation condition monitoring technique for high-frequency applications of silicon carbide power MOSFETs

Gate oxide degradation, which considerably affects turn- on /- off dynamics of the switch, embraces a large percentage of chip-related failure modes both in silicon and silicon carbide power MOSFETs. The gate oxide layer is thinner in silicon carbide power MOSFETs in comparison to their silicon-based counterparts. Consequently, the problem of gate oxide degradation has become a more crucial impediment in achieving reliable performance in silicon carbide power MOSFETs. This problem is even more severe in high-frequency applications due to higher EMI signature and complicated and costly measurement. In this article, a reliable fully analog cost-effective gate oxide degradation condition monitoring technique is proposed and validated. High-order harmonics magnitudes of drain–source voltage are used to produce a dc signal as the aging precursor of the gate oxide region. Using a dedicated degradation setup, the credibility of the developed condition monitoring technique was examined at different rates of gate oxide degradation for 650-V/22-A silicon carbide discrete MOSFET. In 200-kHz, 217-V switch operation, the proposed precursor showed 68% change in comparison to its initial value. This brings a high-resolution assessment on the reliability level of the switch gate oxide region

On the effect of SiC power MOSFET gate oxide degradation in high frequency phase leg-based applications

Silicon Carbide power MOSFET is a promising option for high power high density applications in the next generation of power electronic applications. Investigating the reliability issues and concerns, however, is a pre-requisite for enabling this technology to be widely used. Gate oxide degradation is a major chip-related failure mode in MOSFETs. The problem of gate oxide degradation is even more severe in SiC MOSFETs because of the thin gate-oxide layer. Interface trapped charge at SiCSiO2 interface is much higher than Si counterpart. The main effect of gate oxide degradation is changes in Miller plateau and threshold voltage value of the switch. These changes usually lead to having a longer rise time and shorter fall time in the switch. Although extensive research has been carried out on proposing precursors and characterization for SiC MOSFET gate oxide degradation, a circuit-level study is lacking. In this paper, the effect of gate oxide degradation on the operation of a half-bridge converter is studied. It is shown that the deadtime between the high side and low side switches in phase leg structure has been increased. In high frequency applications with short pulsewidth, the main consequence is that the average load voltage will be decreased. To show the effect of gate oxide degradation on phase leg operation, simulation in PSpice and experimental set-up are used. Commercial discrete SiC MOSFET 650V/22A is degraded in gate oxide layer using an adjustable degradation set-up. The brand-new and degraded switches are examined in a phase leg structure with switching frequency of 115kHz. The results showed that a 45% increment in deadtime is detected, which leads to decrement in the average voltage of the load