Non-Volatile Resistive Switching of Polymer Residues in 2D Material Memristors

Two-dimensional (2D) materials are popular candidates for emerging nanoscale devices, including memristors. Resistive switching (RS) in such 2D material memristors has been attributed to the formation and dissolution of conductive filaments created by the diffusion of metal ions between the electrodes. However, the area-scalable fabrication of patterned devices involves polymers that are difficult to remove from the 2D material interfaces without damage. Remaining polymer residues are often overlooked when interpreting the RS characteristics of 2D material memristors. Here, we demonstrate that the parasitic residues themselves can be the origin of RS. We emphasize the necessity to fabricate appropriate reference structures and employ atomic-scale material characterization techniques to properly evaluate the potential of 2D materials as the switching layer in vertical memristors. Our polymer-residue-based memristors exhibit RS typical for a filamentary mechanism with metal ion migration, and their performance parameters are strikingly similar to commonly reported 2D material memristors. This reveals that the exclusive consideration of electrical data without a thorough verification of material interfaces can easily lead to misinterpretations about the potential of 2D materials for memristor applications.Comment: 30 page

A simple charge and capacitance compact model for asymmetric III-V DGFETs using CCDA

by Mohit D. Ganeriwal

Analysis of Gate Leakage Current in High-k Metal Gate MOS Transistors

"Increased power dissipation is one of the major issue for today’s chip designers. Gate leakage across the gate dielectric being one of the major component leading to power dissipation in circuits it is necessary to have its clear understanding. Due to distinctive properties of HfO2 dielectric, used in advance CMOS devices, the gate current through it is noticeably different from that of the conventional SiO2 dielectric. Literature reports extensive work to understand the gate current mechanism through HfO2 dielectric. However, these studies are either restrictive in terms of the applied bias or the type of MOS transistor. They also do not elaborate on the reasons for change in leakage mechanisms with change in gate voltages. Thus the gate current mechanism through this HfO2 dielectric is still controversial. This work analyses gate current of both nMOS and pMOS transistors with HfO2 dielectric gate stack. Using measurement and simulation studies we presents a theory which could consistently explains the gate leakage for the entire biasing range of both the MOS transistors. This theory also explains the observed temperature dependency shown by the gate current. The gate leakage is shown to be dependent on oxide traps which are generated due to large number of positively charge oxygen vacancies in HfO2. Also the change in energy level of these traps is shown to be responsible for change in leakage mechanism. Further it was shown for the first time in this work that the gate current is anomalously dependent on the width of the devices. The theory presented in this work explains this anomalous width dependency and it is attributed to the annihilation of positively charge oxygen vacancies at the corner of the activegate overlap region."by Mohit D. GaneriwalaM.Tech

An unified charge centroid model for silicon and low effective mass III-V channel double gate MOS transistors

by Amratansh Gupta, Mohit D. Ganeriwala and Nihar Ranjan Mohapatr

Capacitance and surface potential model for III-V double-gate FET

by G.M. Sarath Chandran, Mohit D. Ganeriwala and Nihar Ranjan Mohapatr

Effect of pregate carbon implant on narrow Width behavior and performance of high-k metal-gate nMOS transistors

This paper experimentally shows the reduction of anomalous narrow width effect (NWE) observed in gate-first high- k metal-gate (HKMG) nMOS transistors by using pregate carbon implants. The experiments are performed with different carbon implant doses and energies, in collaboration with a semiconductor foundry. The 28-nm gate-first HKMG CMOS technology is used as the baseline flow. The physical mechanisms responsible for this improvement are identified and explained in detail. It is further shown that the pregate carbon implant used to suppress the NWE also increases junction leakage, improves the device electrostatics, and improves the universal curve.by Nihar R Mohapatra, Mohit D. Ganeriwala and Satya Sivanaresh M