3 research outputs found
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Design of on-line arithmetic networks for signal processing applications : a color filter implementation
Networks of on-line modules for Digital Signal Processing (DSP) applications have been designed and analyzed in many papers. Various arguments have been made for on-line arithmetic over other bit-serial and parallel approaches. However, the majority, if not all of the on-line network implementations presented throughout the literature do not take into account the input and interfacing issues involved when dealing with real applications. Most studies of on-line network implementations are limited to common components of DSP algorithms but do not consider the impact they have on the whole system. This thesis investigates the use of on-line arithmetic in implementing a color image filtering algorithm. A complete analysis of the algorithm takes into account input value ranges, memory requirements, error analysis, and processing throughput. An equal emphasis is placed on what the end-user is to expect. The realization of the image processing algorithm is presented using conventional on-line modules. A comparison to the estimates of parallel and other traditional bit-serial approaches is done. The results show that the on-line implementation saves the designer an overwhelming amount of area as opposed to a strictly parallel implementation and reduces complexity when compared to an implementation using traditional bit-serial modules, while still providing a significant throughput
A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA
This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels
Large Field-Size Elliptic Curve Processor for Area-Constrained Applications
This article has proposed an efficient area-optimized elliptic curve cryptographic processor architecture over GF(2409) and GF(2571). The proposed architecture employs Lopez-Dahab projective point arithmetic operations. To do this, a hybrid Karatsuba multiplier of 4-split polynomials is proposed. The proposed multiplier uses general Karatsuba and traditional schoolbook multiplication approaches. Moreover, the multiplier resources are reused to implement the modular squares and addition chains of the Itoh-Tsujii algorithm for inverse computations. The reuse of resources reduces the overall area requirements. The implementation is performed in Verilog (HDL). The achieved results are provided on Xilinx Virtex 7 device. In addition, the performance of the proposed design is evaluated on ASIC 65 nm process technology. Consequently, a figure-of-merit is constructed to compare the FPGA and ASIC implementations. An exhaustive comparison to existing designs in the literature shows that the proposed architecture utilizes less area. Therefore, the proposed design is the right choice for area-constrained cryptographic applications