Introduction to Hardware Security and Trust

The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society’s microelectronic-supported infrastructures. Provides a comprehensive introduction to hardware security and trust; Includes coverage at the circuit and systems levels, with applications to design and implementation; Describes a variety of state-of-the-art applications, such as physically unclonable functions, unclonable RFID tags and attack and countermeasures for smart cards

Abstract Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design

Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise is increasing. The supply noise is much larger during at-speed delay test compared to normal circuit operation since large number of transitions occur within a short time frame. Existing commercial ATPG tools do not consider the excessive supply noise that might occur in the design during test pattern generation. In this paper, we first present a case study of a SOC design and show detailed IR-drop analysis, measurement and its effects on design performance during at-speed test. We then propose a novel method to measure the average power of at-speed test patterns, referred to as switching cycle average power (SCAP). A new practical pattern generation methodology is proposed to generate supply noise tolerant delay test patterns using existing capabilities in commercial ATPG tools. The results demonstrate that the new patterns generated using our technique will minimize the supply noise effects on path delay

Abstract A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects

Faster-than-at-speed test have been proposed to detect small delay defects. While these techniques increase the test frequency to reduce the positive slack of the path, they exacerbate the already well known issue of IR-drop during test. This may result in false identification of good chips to be faulty due to IR-drop rather than small delay defects. We present a case study of IR-drop effects due to faster-than-at-speed test. We propose a novel framework for pattern generation/application using any commercial no-timing ATPG tool, to screen small delay defects and a technique to determine the optimal test frequency considering both performance degradation due to IR-drop effects and positive slack. 1

Test-Pattern Grading and Pattern Selection for Small-Delay Defects

Timing-related defects are becoming increasingly impor-tant in nanometer technology designs. Small delay vari-ations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can po-tentially cause timing failures in a design, thereby lead-ing to quality and reliability concerns. We present a test-grading technique to leverage the method of output devi-ations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and it excites a larger number of long paths compared to pre-viously proposed timing-aware ATPG methods. We show that, for the same pattern count, the selected patterns are more effective than timing-aware ATPG for detecting small delay defects caused by resistive shorts, resistive opens, and process variations.

A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk

International audienc

Pattern Generation and Estimation for Power-Supply Noise Analysis

This paper presents a new automatic pattern generation methodology to stimulate the maximum power supply noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 � 1 and 1 � 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns were verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum power supply noise