Numerical Insights into the Influence of Electrical Properties of n-CdS Buffer Layer on the Performance of SLG/Mo/p-Absorber/n-CdS/n-ZnO/Ag Configured Thin Film Photovoltaic Devices

A CdS thin film buffer layer has been widely used as conventional n-type heterojunction partner both in established and emerging thin film photovoltaic devices. In this study, we perform numerical simulation to elucidate the influence of electrical properties of the CdS buffer layer, essentially in terms of carrier mobility and carrier concentration on the performance of SLG/Mo/p-Absorber/n-CdS/n-ZnO/Ag configured thin film photovoltaic devices, by using the Solar Cell Capacitance Simulator (SCAPS-1D). A wide range of p-type absorber layers with a band gap from 0.9 to 1.7 eV and electron affinity from 3.7 to 4.7 eV have been considered in this simulation study. For an ideal absorber layer (no defect), the carrier mobility and carrier concentration of CdS buffer layer do not significantly alter the maximum attainable efficiency. Generally, it was revealed that for an absorber layer with a conduction band offset (CBO) that is more than 0.3 eV, Jsc is strongly dependent on the carrier mobility and carrier concentration of the CdS buffer layer, whereas Voc is predominantly dependent on the back contact barrier height. However, as the bulk defect density of the absorber layer is increased from 1014 to 1018 cm−3, a CdS buffer layer with higher carrier mobility and carrier concentration is an imperative requirement to a yield device with higher conversion efficiency and a larger band gap-CBO window for realization of a functional device. Most tellingly, simulation outcomes from this study reveal that electrical properties of the CdS buffer layer play a decisive role in determining the progress of emerging p-type photo-absorber layer materials, particularly during the embryonic device development stage