dRail: a novel physical layout methodology for power gated circuits

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 processor using a 65nm library, and shows up to 38% reduction in area cost when compared to traditional voltage area layou

Leakage power minimisation techniques for embedded processors

Leakage power is a growing concern in modern technology nodes. In some current and emerging applications, speed performance is uncritical but many of these applications rely on untethered power making energy a primary constraint. Leakage power minimisation is therefore key to maximising energy efficiency for these applications. This thesis proposes two new leakage power minimisation techniques to improve the energy efficiency of embedded processors. The first technique, called sub-clock power gating,can be used to reduce leakage power during the active mode. The technique capitalises on the observation that there can be large combinational idle time within the clock period in low performance applications and therefore power gates it. Sub-clock power gating is the first study into the application of power gating within the clock period, and simulation results on post layout netlists using a 90nm technology library show 3.5x, 2x and 1.3x improvement in energy efficiency for three test cases: 16-bit multiplier, ARM Cortex-M0 and Event Processor at a given performance point. To reduce the energy cost associated with moving between the sleep and active mode of operation, a second technique called symmetric virtual rail clamping is proposed. Rather than shutting down completely during sleep mode, the proposed technique uses a pair of NMOS and PMOS transistors at the head and foot of the power gated logic to lower the supply voltage by 2Vth. This reduces the energy needed to recharge the supply rails and eliminates signal glitching energy cost during wake-up. Experimental results from a 65nm test chip shows application of symmetric virtual rail clamping in sub-clock power gating improves energy efficiency, extending its applicable clock frequency range by 400x. The physical layout of power gating requires dedicated techniques and this thesis proposes dRail, a new physical layout technique for power gating. Unlike the traditional voltage area approach, dRail allows both power gated and non-power gated cells to be placed together in the physical layout to reduce area and routing overheads. Results from a post layout netlist of an ARM Cortex-M0 with sub-clock power gating shows standard cell area and signal routing are improved by 3% and 19% respectively. Sub-clock power gating, symmetric virtual rail clamping and dRail are incorporated into power gating design flows and are compatible with commercial EDA tools and gate libraries

Understanding Microbial Loads in Wastewater Treatment Works as Source Water for Water Reuse

Facing challenges in water demands and population size, particularly in the water-scarce regions in the United States, the reuse of treated municipal wastewater has become a viable potential to relieve the ever-increasing demands of providing water for (non-)potable use. The objectives of this study were to assess microbial quality of reclaimed water and to investigate treatability of microorganisms during different treatment processes. Raw and final treated effluent samples from three participating utilities were collected monthly for 16 months and analyzed for various microbial pathogens and fecal indicator organisms. Results revealed that the detectable levels of microbial pathogens tested were observed in the treated effluent samples from all participating utilities. Log10 reduction values (LRVs) of Cryptosporidium oocysts and Giardia cysts were at least two orders of magnitude lower than those of human adenovirus and all fecal indicator organisms except for aerobic endospores, which showed the lowest LRVs. The relatively higher LRV of the indicator organisms such as bacteriophages suggested that these microorganisms are not good candidates of viral indicators of human adenovirus during wastewater treatment processes. Overall, this study will assist municipalities considering the use of wastewater effluent as another source of drinking water by providing important data on the prevalence, occurrence, and reduction of waterborne pathogens in wastewater. More importantly, the results from this study will aid in building a richer microbial occurrence database that can be used towards evaluating reuse guidelines and disinfection practices for water reuse practices