A New Area and Power Efficient Single Edge Triggered Flip-Flop Structure for Low Data Activity and High Frequency Applications

In this work, a new area and power efficient single edge triggered flip-flop has been proposed. The proposed design is compared with six existing flip-flop designs. In the proposed design, the number of transistors is reduced to decrease the area. The number of clocked transistors of the devised flip-flop is also reduced to minimize the power consumption. As compared to the other state of the art single edge triggered flip-flop designs, the newly proposed design is the best energy efficient with the comparable power delay product (PDP) having an improvement of up to 61.53% in view of power consumption. The proposed flip-flop also has the lowest transistor count and the lowest area. The simulation results show that the proposed flip-flop is best suited for low power and low area systems especially for low data activity and high frequency applications. Keywords: PDP, reliability, delay, process node, clock frequenc

Novel Low Power and Low Transistor Count Flip-Flop Design with High Performance

The paper proposed a new design of static SET flip-flop for low power applications. In this work, comparative analysis of existing architecture for flip-flops along with the proposed design is made. The comparison is done on the basis of power and power delay product, transistor count is also included. Due to continuous increase in integration of transistors and growing needs of portable equipments, low power design is of prime importance. The proposed design has the best power and the second best PDP than the existing architectures. Proposed FF has the least transistor count hence reducing the manufacturing cost and area. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, proposed FF has the best power consumption, second best PDP and the lowest transistor count. So this design is best suited for low power and high performance portable applications. Keywords: Transmission Gate, Short circuit current, Edge Triggered, Optimizatio

Social relationship analysis using state-of-the-art embeddings.

Detection of human relationships from their interactions on social media is a challenging problem with a wide range of applications in different areas, like targeted marketing, cyber-crime, fraud, defense, planning, and human resource, to name a few. All previous work in this area has only dealt with the most basic types of relationships. The proposed approach goes beyond the previous work to efficiently handle the hierarchy of social relationships. This article introduces a novel technique named Quantifiable Social Relationship (QSR) analysis for quantifying social relationships to analyze relationships between agents from their textual conversations. QSR uses cross-disciplinary techniques from computational linguistics and cognitive psychology to identify relationships. QSR utilizes sentiment and behavioral styles displayed in the conversations for mapping them onto level II relationship categories. Then, for identifying the level III relationship categories, QSR uses level II relationships, sentiments, interactions, and word embeddings as key features. QSR employs natural language processing techniques for feature engineering and state-of-the-art embeddings generated by word2vec, global vectors (glove), and bidirectional encoder representations from transformers (bert). QSR combines the intrinsic conversational features with word embeddings for classifying relationships. QSR achieves an accuracy of up to 89% for classifying relationship subtypes. The evaluation shows that QSR can accurately identify the hierarchical relationships between agents by extracting intrinsic and extrinsic features from textual conversations between agents

Design of Semi-Static SET Flip-Flop for Low Power and High Performance Applications

Abstract — The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. The simulation results show that for all supply voltages, all clock frequencies and all data activities, the proposed flip-flop has the better power consumption than all the six existing flip-flops discussed in this paper. The proposed flip-flop also shows the second lowest PDP and the second shortest delay