On the multiplicity of Laplacian eigenvalues of graphs

summary:In this paper we investigate the effect on the multiplicity of Laplacian eigenvalues of two disjoint connected graphs when adding an edge between them. As an application of the result, the multiplicity of 1 as a Laplacian eigenvalue of trees is also considered

Unified tensor network theory for frustrated classical spin models in two dimensions

Frustration is a ubiquitous phenomenon in many-body physics that influences the nature of the system in a profound way with exotic emergent behavior. Despite its long research history, the analytical or numerical investigations on frustrated spin models remain a formidable challenge due to their extensive ground state degeneracy. In this work, we propose a unified tensor network theory to numerically solve the frustrated classical spin models on various two-dimensional (2D) lattice geometry with high efficiency. We show that the appropriate encoding of emergent degrees of freedom in each local tensor is of crucial importance in the construction of the infinite tensor network representation of the partition function. The frustrations are thus relieved through the effective interactions between emergent local degrees of freedom. Then the partition function is written as a product of a one-dimensional (1D) transfer operator, whose eigen-equation can be solved by the standard algorithm of matrix product states rigorously, and various phase transitions can be accurately determined from the singularities of the entanglement entropy of the 1D quantum correspondence. We demonstrated the power of our unified theory by numerically solving 2D fully frustrated XY spin models on the kagome, square and triangular lattices, giving rise to a variety of thermal phase transitions from infinite-order Brezinskii-Kosterlitz-Thouless transitions, second-order transitions, to first-order phase transitions. Our approach holds the potential application to other types of frustrated classical systems like Heisenberg spin antiferromagnets.Comment: 20 pages, 19 figure

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.Comment: ACM/IEEE Design Automation Conference (DAC), 201