Field Division Routing

Abstract—Multi-hop communication objectives and constraints impose a set of challenging requirements that create difficult conditions for simultaneous optimization of features such as scalability and performance. We have developed field division routing (FDR), a distributed and nonhierarchical routing protocol that aims to coordinated addressing of scalability, topology alternations, latency, throughput, energy efficiency, and local storage requirements. FDR is based upon two optimization mechanisms: a reactive and focused diffusion that collects only network topology information directly required for making localized routing decisions, and a protocol for sharing routing information among neighboring nodes. Routing table initialization and maintenance are scalable in terms of both storage and overhead traffic. FDR provides guaranteed connectivity while providing near-optimal all-node-pairs message delivery. The protocol is also power-efficient to a wide spectrum of topology changes that induce relatively few messages to update routing tables networkwide. We analyzed FDR both theoretically and using simulation. Index Terms—Ad-hoc networks, routing, multi-hop communication. I

PPMexe: Program Compression

With the emergence of software delivery platforms, code compression has become an important system component that strongly affects performance. This article presents PPMexe, a compression mechanism for program binaries that analyzes their syntax and semantics to achieve superior compression ratios. We use the generic paradigm of prediction by partial matching (PPM) as the foundation of our compression codec. PPMexe combines PPM with two preprocessing steps: (i) instruction rescheduling to improve prediction rates and (ii) heuristic partitioning of a program binary into streams with high autocorrelation. We improve the traditional PPM algorithm by (iii) using an additional alphabet of frequent variable-length supersymbols extracted from the input stream of fixed-length symbols. In addition, PPMexe features (iv) a low-overhead mechanism that enables decompression starting from an arbitrary instruction of the executable, a property pivotal for runtime software delivery. We implemented PPMexe for x86 binaries and tested it on several large applications. Binaries compressed using PPMexe were 18–24 % smaller than files created using off-the-shelf PPMD, one of the best available compressors

HypermediaAided Design

Recently, the Internet revolutionized many activities from entertainment to marketing and business. Two key underlying Internet technologies, efficient data delivery and hypertext, demonstrated exceptional potential as new application enablers. In this paper, we present a novel Hypermedia-Aided Design (HAD) collaboration framework that facilitates new communication and data presentation paradigms to improve the effectiveness of typical EDA applications. The framework leverages on the advantages of using semantic multicast as a communication backbone and quantized hypermedia presentations as an efficient data organization, retrieval, and presentation model. Semantic multicast is a global communication tool that relies on an internetwork of proxies to provide content discovery and semanticsbased profile-driven data dissemination services. We introduce the notion of a quant, an atomic interactive multimedia information primitive with embedded hyperlinks. We demonstrate how interest-specific quant retrieval and concatenation can enable more focused collaboration. The HAD framework consists of a set of applications for student(designer)-centered CAD education(consulting), collaborative design and debugging, I-commerce, and technical support. In all applications, quant-based presentations enable that theoretical and practical components are tailored according to user's interest and performances. The conceptualized and implemented applications act in synergy with existing software, hardware, and system design tools. 1

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, NO., DATE 1 Latency-Guided On-Chip Bus Network Design

Abstract — Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, ultra-high level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity and increased communication demands. The convergence of these two factors emphasizes the importance of the on-chip bus network as one of the crucial high-performance enablers for future systems-on-chip. We have developed an on-chip bus network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design. The approach has three components: a communication profiler, a bus network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus network design component optimizes the bus network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan; it also sends feedback about the most constrained parts of the network. We demonstrate the effectiveness of our bus network design approach on a number of multi-core designs. Index Terms — Bus network design, latency, system synthesis, on-chip communication