Instruction-Level Distributed Processing

has emphasized instruction-level parallelism, which improves performance by increasing the number of instructions per cycle. In striving for such parallelism, researchers have taken microarchitectures from pipelining to superscalar processing, pushing toward increasingly parallel processors. They have concentrated on wider instruction fetch, higher instruction issue rates, larger instruction windows, and increasing use of prediction and speculation. In short, researchers have exploited advances in chip technology to develop complex, hardware-intensive processors. Benefiting from ever-increasing transistor budgets and taking a highly optimized, “big-compile ” view of software, microarchitecture researchers made significant progress through the mid-1990s. More recently, though, researchers have seemingly reduced the problem to finding ways of consuming transistors, resulting in hardware-intensive, complex processors. The complexity is not just in critical path lengths and transistor counts: There is high intellectual complexity in the increasingly intricate schemes for squeezing performance out of second- and third-order effects. Substantial shifts in hardware technology and software applications will lead to general-purpose microarchitectures composed of small, simple, interconnected processing elements, running at very high clock frequencies. A hidden layer of implementationspecific software—co-designed with the hardware— will help manage the distributed hardware resources to use power efficiently and to dynamically optimize executing threads based on observed instruction dependencies and communication. COVER FEATUR