10 research outputs found
An address generation unit for a processor (priority date 07-05-2003/international filing date 07-05-2003/international publication date 09-03-2005)
No full textAn address generation unit for a processor (priority date 07-05-2003/international filing date 07-05-2003/international publication date 09-03-2005)
No full textDevice and method for composing codes (priority date 23-07-2003/international filing date 13-07-2004/international publication date 27-01-2005)
No full textA scalar/vector processor (priority date 24-05-2002/international filing date 22-05-2003/international publication date 09-03-2005)
No full textDevice and method for composing codes (priority date 23-07-2003/international filing date 13-07-2004/international publication date 27-01-2005)
No full textA scalar/vector processor (priority date 24-05-2002/international filing date 22-05-2003/international publication date 09-03-2005)
No full text
Vector processing as an enabler for software-defined radio in handsets from 3G+WLAN onwards
No full textVector processing as an enabler for software-defined radio in handheld devices
Get PDFA major challenge of software-defined radio (SDR) is to realize many giga operations per second of flexible baseband processing within a power budget of only a few hundred mW. A heterogeneous hardware architecture with the programmable vector processor EVP as key component can support WLAN, UMTS, and other standards. A detailed rationale for the EVP architecture, based on the analysis of a number of key algorithms, as well as implementation and benchmarking results are described
