Memory cell structure integrated on semiconductor

This invention relates to a memory cell Which comprises a capacitor having a ?rst electrode and a second electrode separated by a dielectric layer. Such dielectric layer com prises a layer of a semi-insulating material Which is fully enveloped by an insulating material and in Which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the ?rst or to the second electrode, depending on the electric ?eld betWeen the electrodes,therebyde?ningdifferentlogiclevels

Reliability and retention study of nanocrystal cell array

We have studied nanocrystal memory arrays with 2.56×105 cells (256kb) in which Si nanocrystals have been obtained by CVD deposition on a 4nm tunnel oxide. The cells in the array are programmed and erased by electron tunneling through the SiO2 dielectric. We find that the threshold voltage distribution has little spread. In addition the arrays are also very robust with respect to drain stress and show good retention

Effects of nitridation by N2O or NO on the electrical properties of thin gate or tunnel oxides

We have studied the effects of nitridation on the leakage current of thin (7-8 nm) gate or tunnel oxides. A polarity dependence of the tunneling current has been found this behavior is related to the presence of a thin silicon oxynitride layer at the SiO2/Si-substrate interface. The oxynitride layer lowers the tunneling current when electrons are injected from the interface where the oxynitride is located (substrate injection). The current flowing across the oxide when electrons are injected from the opposite interface (gate injection) is not influenced by the oxynitride. The increase of nitrogen concentration leads to a decrease of the tunneling current for substrate electron injection

Memory effects in single-electron nanostructures

We investigate the memory function at room temperature in devices based on quantum dots. By Low Pressure Chemical Vapour Deposition (LPCVD) we deposited Si dots embedded in SiO2. On these devices flat band voltage shifts were well detected at low write voltages for write times of the order of milliseconds, and furthermore, a plateau in the flat band voltage shift, maybe consequence of Coulomb blockdale, was observed

Nanocrystal MOS with silicon-rich oxide

By electrical measurements we investigate the charge trapping and the charge transport in MOS capacitors in which the gate oxide has been replaced with a silicon rich oxide (SRO) film sandwiched between two thin SiO2 layers

Location of holes in silicon-rich oxide as memory states

The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh time compared to conventional dynamic random access memory cells. © 2002 American Institute of Physics

Peculiar aspects of nanocrystal memory cells: Data and extrapolations

Nanocrystal memory cell are a promising candidate for the scaling of nonvolatile memories in which the conventional floating gate is replaced by an array of nanocrystals. The aim of this paper is to present the results of a thorough investigation of the possibilities and the limitations of such new memory cell. In particular, we focus on devices characterized by a very thin tunnel oxide layer and by silicon nanocrystals formed by chemical vapor deposition. The direct tunneling of the electrons through the tunnel oxide, their storage into the silicon nanocrystals, and furthermore, retention, endurance, and drain turn-on effects, well-known issues for nonvolatile memories, are all investigated. The cell can be also programmed by channel hot electron injection, allowing the possibility to multibit storage. The suppression of the drain turn-on and the possibility of using this cell for multibit storage give us a clear evidence of the distributed nature of the charge storage

Memory effects in MOS capacitors with silicon quantum dots

To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials have been annealed in N2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory functions of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO2 layers as insulator and with an n+ polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance-voltage characteristics. A model which explains both the occurence of steady-state conduction through the SiO2/SRO/SiO2 stack at a relatively low voltage and the shift of flat-band voltage is presented and discussed. © 2001 Elsevier Science B.V. All rights reserved

Multi-bit storage through Si nanocrystals embedded in SiO2

We have realized Si nanocrystal memory cells in which the Si dots have been deposited by CVD on SiO2 and then covered by a CVD control oxide. In this paper, we report a study on the potential of these cells for dual bit storage. © 2004 Elsevier B.V. All rights reserved