Instruction set extensions for software defined radio on a multithreaded processor

Software dened radios, which provide a programmable solu-tion for implementing the physical layer processing of multi-ple communication standards, are widely recognized as one of the most important new technologies for wireless com-munication systems. Emerging communication standards, however, require tremendous processing capabilities to per-form high-bandwidth physical-layer processing in real time. In this paper, we present instruction set extensions for sev-eral important communication algorithms including convo-lutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. The performance bene ts of these extensions are evaluated using a supercom-puter class vectorizing compiler and the Sandblaster low-power multithreaded processor for software dened radio. The proposed instruction set extensions provide signicant performance improvements, while maintaining a high degree of programmability. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-purpose and Application-based Systems|Real-time and embedded sys

Implementing and Exploiting Static Speculation on Multiple Instruction Issue Processors

Trends in processor architecture and design suggest that static speculation will become a candidate for implementation on future high-performance processors. In this dissertation, we shall examine issues related to the implementation and exploitation of static speculation. There are four primary results: 1) Precise Exceptions: Prior work in static speculation has not examined the interaction between exception handling and speculative instructions in any great detail. We investigate this interaction, exhibiting certain problematic subtleties that arise, and show how they can be overcome. 2) Speculative Tagging: Earlier proposals for implementing speculative instructions tended to have several drawbacks, including restricted applicability. We introduce speculative tagging, a new, more general, mechanism for specifying static speculation, and show it is possible to optimize exception recovery through this mechanism. 3) Whole-DAG Scheduling: Recently, there has been some work on scheduling regions of acyclic code larger than a basic block so as to take advantage of static speculation. We describe another such algorithm, known as whole-DAG scheduling, that contains innovations that make it more flexible, and allow it to use better heuristics. 4) Dynamic Speculation: The work on static speculation and exceptions suggested an alternative approach to implementing dynamic speculation. This approach results in simpler hardware than prior schemes, and is consequently cheaper to implement and potentially has a lesser impact on cycle-time. Additionally, we report results of experimental studies measuring the effectiveness of whole-DAG scheduling. In it, we show, among other things, that our scheduling technique can result in near-optimal schedules, and that the selection heuristics we adopt are superior to those used in earlier algorithms

ABSTRACT Wireless SDR Solutions: The Challenge and Promise of Next Generation Handsets

In this paper, some aspects of implementing convergence devices in software are described. First, the motivation for Software Defined Radio (SDR) solutions. including market drivers, is discussed. Next, a technical introduction to high-complexity wireless applications is presented. The Sandbridge solution to multimode baseband processing is described, including an SDR processor architecture and results. We then present a solution that provides a 768kbps WCDMA compliant transmit in less than 400MHz on the Sandblaster TM multithreaded processor

Mechanisms for Specifying Static Speculation

We first review boosting and exception-tag bits, two mechanisms for specifying static speculation. We then introduce speculative tagging which introduces a new resource, the speculative tags, for specifying and controlling static speculation of instructions. Each speculative instruction is associated with a tag, and its result is accepted or discarded depending on whether its tag is committed or flushed. We compare the capabilities of the three schemes, and conclude that speculative tagging is strictly more powerful than both boosting and the exception-tag bit schemes. 1 Introduction It is well-known that the performance of instruction level parallel processors is improved if the processor is allowed to speculatively issue instructions (i.e. issue an instruction from below a branch, before it is known whether the branch will be taken). In most processor implementations speculation has been performed dynamically by the hardaware see for example [1, 5, 3, 4, 13, 12]. The hardware requi..

Galois Field Instructions in the Sandblaster 2.0 Architectrue

This paper presents a novel approach to implementing multiplication of Galois Fields with 2N. Elements of GF(2N) can be represented as polynomials of degree less than N over GF(2). Operations are performed modulo an irreducible polynomial of degree n over GF(2). Our approach splits a Galois Field multiply into two operations, polynomial-multiply and polynomial-remainder over GF(2). We show how these two operations can be implemented using the same hardware. Further, we show that in many cases several polynomial-multiply operations can be combined before needing to a polynomial-remainder. The Sandblaster 2.0 is a SIMD architecture. It has SIMD variants of the poly-multiply and poly-remainder instructions. We use a Reed-Solomon encoder and decoder to demonstrate the performance of our approach. Our new approach achieves speedup of 11.5x compared to the standard SIMD processor of 8x

Register Renaming and Dynamic Speculation: an Alternative Approach

In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instruction fetch stage instead of the decode stage, and the mechanism is designed to operate in parallel with the tag match logic used by most cache designs. It is estimated that the critical path of the mechanism requires approximately the same number of logic levels as the tag match logic, and therefore should not impact cycle time. 1 Introduction Superscalar processors attempt to exploit instruction level parallelism by issuing multiple instructions in parallel, thereby improving performance. This improvement is limited by the amount of fine-grain parallelism present in the code. Several mechanisms have been developed that increase the number of instructions that a processor can issue in parallel, thereby increasing performance. This paper focuses on two such mechanisms: register renaming and dynamic speculation. A..