TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model

Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3MIPS using the Dhrystone V2.1 benchmark. 1 Introduction Projecting forward from today, several reports suggest that, in 10 years, the CMOS technology will reach a point where the switching delay for a single gate is close to 10 picoseconds while a single chip area is nearly 10 square centimeters, with wiring moving into dominance[1]. The dominant wiring delay poses a fundamental limitation on synchronous syste..