Increase in Interference Levels in the 45 -- 870 MHz Band at the Spanish e-CALLISTO Sites over the Years 2012 and 2019

Two sets of radio-frequency interference (RFI) measurements in the 45 ? 870 MHz band are compared. The first set was taken in 2012 at various sites in the province of Guadalajara (Spain) as part of a worldwide site-testing campaign for the deployment of an international network of solar radio-spectrometers, the Compound Astronomical Low-cost Low-frequency Instrument for Spectroscopy and Transportable Observatory (e-CALLISTO) array. Peralejos de las Truchas was found to be an ideal location, even for high-sensitivity non-solar observations, with the lowest interference levels ever measured in the framework of e-CALLISTO. The same set of measurements have been repeated seven years later us- ing the same experimental setup at the same locations. The results presented in this article show that the RFI levels after seven years have notably increased, at some places by a factor of two, thereby placing at risk broadband spectroscopic radio-astronomy studies from the ground.Ministerio de Economía y Competitivida

Memory management unit for hardware-assisted dynamic relocation in on-board satellite systems

Satellite on-board systems spend their lives in hostile environments, where radiation can cause critical hardware failures. One of the most radiation-sensitive elements is memory. The so-called single event effects (SEEs) can corrupt or even irretrievably damage the cells that store the data and program instructions. When one of these cells is corrupted, the program must not use it again during execution. In order to avoid rebuilding and uploading the code, a memory management unit can be used to transparently relocate the program to an error-free memory region. This article presents the design and implementation of a memory management unit that allows the dynamic relocation of on-board software. This unit provides a hardware mechanism that allows the automatic relocation of sections of code or data at run-time, only requiring software intervention for initialization and configuration. The unit has been implemented on the LEON architecture, a reference for the European Space Agency (ESA) missions. The proposed solution has been validated using the boot and application software (ASW) of the instrument control unit of the Energetic Particle Detector of the Solar Orbiter Mission as a base. Processor synthesis on different FPGAs has shown resource usage and power consumption similar to that of a conventional memory management unit. The results vary between ± 1?15% in resource usage and ± 1?7% in power consumption, depending on the number of inputs assigned to the unit and the FPGA used. When comparing performance, both the proposed and conventional memory management units show the same results.Universidad de Alcal

A RISC-V Processor Design for Transparent Tracing

Code instrumentation enables the observability of an embedded software system during its execution. A usage example of code instrumentation is the estimation of “worst-case execution time” using hybrid analysis. This analysis combines static code analysis with measurements of the execution time on the deployment platform. Static analysis of source code determines where to insert the tracing instructions, so that later, the execution time can be captured using a logic analyser. The main drawback of this technique is the overhead introduced by the execution of trace instructions. This paper proposes a modification of the architecture of a RISC pipelined processor that eliminates the execution time overhead introduced by the code instrumentation. In this way, it allows the tracing to be non-intrusive, since the sequence and execution times of the program under analysis are not modified by the introduction of traces. As a use case of the proposed solution, a processor, based on RISC-V architecture, was implemented using VHDL language. The processor, synthesized on a FPGA, was used to execute and evaluate a set of examples of instrumented code generated by a “worst-case execution time” estimation tool. The results validate that the proposed architecture executes the instrumented code without overhead