SiGe BiCMOS technology with embedded through-silicon vias and interposer fan-out wafer-level packaging platform

In this paper, the latest developments of a high performance SiGe BiCMOS technology with embedded Through-Silicon Vias and an additional Fan-out Wafer-level Packaging platform based on a silicon interposer and direct wafer bonding are demonstrated. The combination of a SiGe BiCMOS technology including heterojunction bipolar transistors with fmax values of ~500 GHz together with the aforementioned packaging technology modules are explained. Both SiGe BiCMOS with monolithically integrated TSVs together with interposer and a novel Al-Al wafer bonding integration technique are realized to provide high performance and low-cost packaging platforms for mm-wave and THz 2.5/3D heterogeneous integration

A sub-atmospheric chemical vapor deposition process for deposition of oxide liner in high aspect ratio through silicon vias

The formation of a Through Silicon Via (TSV) includes a deep Si trench etching and the formation of an insulating layer along the high-aspect-ratio trench and the filling of a conductive material into the via hole. The isolation of the filling conductor from the silicon substrate becomes more important for higher frequencies due to the high coupling of the signal to the silicon. The importance of the oxide thickness on the via wall isolation can be verified using electromagnetic field simulators. To satisfy the needs on the Silicon dioxide deposition, a sub-atmospheric chemical vapor deposition (SA-CVD) process has been developed to deposit an isolation oxide to the walls of deep silicon trenches. The technique provides excellent step coverage of the 100 mu m depth silicon trenches with the high aspect ratio of 20 and more. The developed technique allows covering the deep silicon trenches by oxide and makes the high isolation of TSVs from silicon substrate feasible which is the key factor for the performance of TSVs for mm-wave 3D packaging

Development of a through-silicon via (TSV) process module for multi-project wafer SiGe BiCMOS and silicon interposer

In this work, the development of a Through-Silicon Via process module for multi-project wafer SiGe BiCMOS and silicon interposer is demonstrated. The TSV technology based on a via-middle approach is optimized to provide TSV process and design flexibility which is required for a multi-project wafer service. Different passive and active TSV-based components like a low-noise amplifier, RF interposer transmission lines and substrate-integrated waveguides are fabricated. The TSV process module enables a wide range of promising new applications by adding additional functionalities to conventional BiCMOS and interposer substrate technologies

Design Optimization of Through-Silicon Vias for Substrate-Integrated Waveguides embedded in High-Resistive Silicon Interposer

International audienceIn this work, the optimization of TSVs for SIWs embedded in a high-resistive silicon interposer is demonstrated. EM simulations are performed to analyze and optimize important TSV design parameters enabling silicon interposer technologies with low-loss SIWs working at mm-wave/THz frequencies. A silicon interposer using high resistive silicon and TSVs is fabricated and SIWs are characterized working from 110-170 GHz with very low attenuation of ~0.5 dB/mm

BiCMOS Integrated Microfluidic Packaging by Wafer Bonding for Lab-on-Chip Applications

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BiCMOS Embedded Microfluidic Technology Based on Wafer Bonding Techniques for Biosensor Applications

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