Modeling and optimization of BiCMOS embedded through-silicon vias for RF-grounding

In this paper we demonstrate the modeling and optimization of BiCMOS embedded high aspect ratio through-silicon vias (TSV) for RF-grounding applications. The inductance and the resistance of the TSV are analyzed with respect to TSV design parameters and process effects such as sidewall-tilting and void formation. RF measurement results with extracted inductance and resistance of 24 pH and 86 m for a single TSV are in very good agreement with the simulation results. Based on the simulated and measured results, RLC-lumped-element models are developed considering the aforementioned process characteristics to provide realistic models for Process-Design-Kit (PDK) implementation

Through-Silicon Via process module with backside metallization and redistribution layer within a 130 nm SiGe BiCMOS technology

The development of a Through-Silicon Via process module within a high performance SiGe BiCMOS technology is demonstrated. The TSV technology module including both the TSV fabrication process itself, the temporary wafer bonding for BiCMOS thin wafer handling and the thin wafer backside processing is developed on 8-inch wafer level and the optimization of the different process steps are explained. This process module is fully compatible with the qualified SiGe BiCMOS technology environment which enables very uniform and reliable TSV backside fabrication adding new functionalities into IHPs high performance SiGe BiCMOS technologies applicable for thin wafer applications and 3D heterogeneous integration

Si1-xGex/Si MQW based uncooled microbolometer development and integration into 130 nm BiCMOS technology

In this paper, the recent progress on Sii-xGeVSi based high performance detector structures is presented. The process optimization of the detector by means of high TCR, low 1/f noise and appropriate resistance is summarized. The method of integrating the developed Sii-xGex/Si multi quantum well (MQW) detector structures into a 130 nm BiCMOS process is provided. The optimization studies required for the full integration of the suspended uncooled microbolometer device are presented

MEMS module integration into SiGe BiCMOS technology for embedded system applications

Different MEMS process techniques have been integrated to 0.25 m BiCMOS process for embedded system applications. Back-End-Off-Line (BEOL) integration technique was developed using standard metallization layers of BiCMOS process with additional MEMS process steps. As an example, an RF-MEMS capacitive switch was realized using BEOL embedded MEMS module. Backside substrate etch method was developed as another MEMS integration technique. This technique is demonstrated by several high-Q passive components which can prevent from substrate losses and on-chip antennas/sensors for multi-GHz applications. Lastly, thick copper metallization with low-k BCB dielectric material was developed and processed on top of BiCMOS BEOL. It provides 2 additional thick copper metallization layers and allows realizing high-Q passives and on-chip THz resonators. Several design examples realized by using developed MEMS modules and processing techniques were also analyzed