Characterisation of thermal and coupling effects in advanced silicon MOSFETs

PhD ThesisNew approaches to metal-oxide-semiconductor field effect transistor (MOSFET) engineering emerge in order to keep up with the electronics market demands. Two main candidates for the next few generations of Moore’s law are planar ultra-thin body and buried oxide (UTBB) devices and three-dimensional FinFETs. Due to miniature dimensions and new materials with low thermal conductivity, performance of advanced MOSFETs is affected by self-heating and substrate effects. Self-heating results in an increase of the device temperature which causes mobility reduction, compromised reliability and signal delays. The substrate effect is a parasitic source and drain coupling which leads to frequency-dependent analogue behaviour. Both effects manifest themselves in the output conductance variation with frequency and impact analogue as well as digital performance. In this thesis self-heating and substrate effects in FinFETs and UTBB devices are characterised, discussed and compared. The results are used to identify trade-offs in device performance, geometry and thermal properties. Methods how to optimise the device geometry or biasing conditions in order to minimise the parasitic effects are suggested. To identify the most suitable technique for self-heating characterisation in advanced semiconductor devices, different methods of thermal characterisation (time and frequency domain) were experimentally compared and evaluated alongside an analytical model. RF and two different pulsed I-V techniques were initially applied to partially depleted silicon-on-insulator (PDSOI) devices. The pulsed I-V hot chuck method showed good agreement with the RF technique in the PDSOI devices. However, subsequent analysis demonstrated that for more advanced technologies the time domain methods can underestimate self-heating. This is due to the reduction of the thermal time constants into the nanosecond range and limitations of the pulsed I-V set-up. The reduction is related to the major increase of the surface to volume ratio in advanced MOSFETs. Consequently the work showed that the thermal properties of advanced semiconductor devices must be characterised within the frequency domain. For UTBB devices with 7-8 nm Si body and 10 nm ultra-thin buried oxide (BOX) the analogue performance degradation caused by the substrate effects can be stronger than the analogue performance degradation caused by self-heating. However, the substrate effects can be effectively reduced if the substrate doping beneath the buried ii oxide is adjusted using a ground plane. In the MHz – GHz frequency range the intrinsic voltage gain variation is reduced ~6 times when a device is biased in saturation if a ground plane is implemented compared with a device without a ground plane. UTBB devices with 25 nm BOX were compared with UTBB devices with 10 nm BOX. It was found that the buried oxide thinning from 25 nm to 10 nm is not critical from the thermal point of view as other heat evacuation paths (e.g. source and drain) start to play a role. Thermal and substrate effects in FinFETs were also analysed. It was experimentally shown that FinFET thermal properties depend on the device geometry. The thermal resistance of FinFETs strongly varies with the fin width and number of parallel fins, whereas the fin spacing is less critical. The results suggest that there are trade-offs between thermal properties and integration density, electrostatic control and design complexity, since these aspects depend on device geometry. The high frequency substrate effects were found to be effectively reduced in devices with sub-100 nm wide fins.Engineering and Physical Sciences Research Council (EPSRC) and EU fundin

RF extraction of self-heating effects in FinFETs of various geometries

Dynamic self-heating effect is characterised in n-channel FinFETs on Silicon-on-Insulator (SOI) platform. RF extraction technique is discussed and dependence of thermal resistance on fin width, number of parallel fins and fin spacing is studied

Time and Frequency Domain Characterization of Transistor Self-Heating

Pulsed I–V and AC conductance or RF characterization techniques, within the time and the frequency domain, respectively, represent two approaches for evaluating self-heating in MOSFETs. In this paper, these methods are compared. Advantages and limitations of each technique are discussed and experimentally verified in silicon-on-insulator (SOI) MOSFETs. It is demonstrated that RF technique and the pulsed I–V hot chuck method agree well for the studied 130-nm-node partially depleted SOI devices. Applicability of the techniques for advanced technologies is discussed

Perspectives of UTBB FD SOI MOSFETs for Analog and RF Applications

Ultra-thin body and buried oxide (UTBB) fully depleted (FD) silicon-on-insulator (SOI) MOSFETs are widely recognized as a promising candidate for 20 nm technology node and beyond, due to outstanding electrostatic control of short channel effects (SCE). Introduction of a highly-doped layer underneath thin buried oxide (BOX), so called ground-plane (GP), targets suppression of detrimental parasitic substrate coupling and opens multi-threshold voltage (V Th ) and dynamic-V Th opportunities within the same process as well as the use of back-gate control schemes [1, 2]. Electrostatics, scalability and variability issues in UTBB MOSFETs as well as their perspectives for low power digital applications are widely discussed in the literature [1–5]. At the same time assessment of UTBB FD SOI for analog and RF applications received less attention. This chapter will discuss Figures of Merit (FoM) of UTBB MOSFETs of interest for further analog/RF applications summarizing our original research over the last years [6–15]. Device analog/RF performance is assessed through the key parameters such as the transconductance, g m , the output conductance, g d , the intrinsic gain, A v and the cut-off frequencies, f T and f max. Particular attention is paid to (1) a wide-frequency band assessment, the only approach that allows fair performance prediction for analog/RF applications; (2) the effect of parasitic elements, whose impact on the device performance increases enormously in deeply downscaled devices, in which they can even dominate device performance. Whenever possible, we will compare FoM achievable in UTBB FD SOI devices with those reported for other advanced device

A SPDT RF Switch Small- and Large-Signal Characteristics on TR-HR SOI Substrates

This paper evaluates the small- and large-signal characteristics of a single pole double thru (SPDT) RF antenna switch including its insertion loss, isolation and non-linear behavior. It is fabricated on three different types of high resistivity (HR) Silicon-on- Insulator (SOI) substrates: one standard (HR-SOI) and two trap-rich (RFeSI80 and RFeSI90). Using a special test structure, the contribution of substrate and active devices is separated for both in small- and large-signal. It is shown that by using trap-rich substrate technology, a reduction of more than 16 dB of 2nd harmonic is achieved compared with HR SOI substrate. In off-state, it is shown that 35 dB increase of harmonic level is due to the non-linearity of active devices. The effect of body bias on small- and large-signal FoMs of the SPDT is investigated and discussed. It is illustrated that trap-rich HR-SOI substrates having much thinner BOX, still outperform classical HRSOI wafer

Comparison of self-heating and its effect on analogue performance in 28 nm bulk and FDSOI

In this work self-heating and its effect on analogue device parameters are compared in 28 nm technology bulk and FDSOI MOS devices. It is shown that for self-heating characterisation in advanced MOSFETs the RF extraction technique is more suitable than the pulsed I–V. It is found that the thermal resistance is ~3.4 times higher and the temperature rise is ~2.5 times higher in 28 nm gate length FDSOI than in bulk. However, in spite of stronger self-heating, FDSOI devices outperform bulk over a wide frequency range. Moreover, device parameters degradation with temperature is attenuated in FDSOI transistors

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects

Trigate nanowire MOSFETs analog figures of merit

This work studies, for the first time to our best knowledge, the perspectives of trigate nanowire (TGNW) MOSFETs for analog applications. An effect of nanowire width, length and orientation as well as frequency (up to 4 GHz) and temperature (up to 225°C) on analog figures-of-merit (FoM) is analyzed. Benchmarking with other advanced devices such as ultra-thin body and BOX (UTBB) MOSFETs and SOI-based FinFETs is presented. TGNW MOSFETs are shown to be very promising for analog applications featuring high transconductance combined with high intrinsic gain. Only a slight reduction of device performance over the frequency and temperature ranges is observed

RF extraction of self-heating effects in FinFETs of various geometries

Dynamic self-heating effect is characterised in n-channel FinFETs on Silicon-on-Insulator (SOI) platform. RF extraction technique is discussed and dependence of thermal resistance on fin width, number of parallel fins and fin spacing is studied