Optimization of Gate Leakage and NBTI for Plasma-Nitrided Gate Oxides by Numerical and Analytical Models

Reduction in static-power dissipation (gate leakage) by using nitrided oxides comes at the expense of enhanced negative-bias temperature instability (NBTI). Therefore, determining the nitrogen content in gate oxides that can simultaneously optimize gate-leakage and NBTI degradation is a problem of significant technological relevance. In this paper, we experimentally and theoretically analyze wide range of gate-leakage and NBTI stress data from a variety of plasma-oxynitride gate dielectric devices to establish an optimization scheme for gate-leakage and NBTI degradation. Calculating electric fields and leakage current both numerically and using simple analytical expressions, we demonstrate a design diagram for arbitrary nitrogen concentration and effective oxide thickness that may be used for process and IC design

A common framework of NBTI generation and recovery in plasma-nitrided SiON p-MOSFETs

Generation and recovery of degradation during and after negative bias temperature instability (NBTI) stress are studied in a wide variety of plasma-nitrided (PN) silicon oxynitride (SiON) p-MOSFETs. An ultrafast on-the-fly linear drain current (IDLIN) technique, which is capable of measuring the shift in threshold voltage from very short (approximately in microseconds) to long (approximately in hours) stress/ recovery time, is used. The mechanics of NBTI generation and recovery are shown to be strongly correlated and can be consistently explained using the framework of an uncorrelated sum of a fast and weakly temperature (T)-dependent trapped-hole (Vh) component and a relatively slow and strongly T-activated interface trap (VIT) component. The SiON process dependences are attributed to the difference in the relative contributions of Vh and VIT to the overall degradation (VT), as dictated by the nitrogen (N) content and thickness of the gate insulator

Robust estimation of bacterial cell count from optical density

Optical density (OD) is widely used to estimate the density of cells in liquid culture, but cannot be compared between instruments without a standardized calibration protocol and is challenging to relate to actual cell count. We address this with an interlaboratory study comparing three simple, low-cost, and highly accessible OD calibration protocols across 244 laboratories, applied to eight strains of constitutive GFP-expressing E. coli. Based on our results, we recommend calibrating OD to estimated cell count using serial dilution of silica microspheres, which produces highly precise calibration (95.5% of residuals <1.2-fold), is easily assessed for quality control, also assesses instrument effective linear range, and can be combined with fluorescence calibration to obtain units of Molecules of Equivalent Fluorescein (MEFL) per cell, allowing direct comparison and data fusion with flow cytometry measurements: in our study, fluorescence per cell measurements showed only a 1.07-fold mean difference between plate reader and flow cytometry data

Fundamentals of bias temperature instability in MOS transistors: characterization methods, process and materials impact, DC and AC modeling

This book aims to cover different aspects of Bias Temperature Instability (BTI). BTI remains as an important reliability concern for CMOS transistors and circuits. Development of BTI resilient technology relies on utilizing artefact-free stress and measurement methods and suitable physics-based models for accurate determination of degradation at end-of-life, and understanding the gate insulator process impact on BTI. This book discusses different ultra-fast characterization techniques for recovery artefact free BTI measurements. It also covers different direct measurements techniques to access pre-existing and newly generated gate insulator traps responsible for BTI. The book provides a consistent physical framework for NBTI and PBTI respectively for p- and n- channel MOSFETs, consisting of trap generation and trapping. A physics-based compact model is presented to estimate measured BTI degradation in planar Si MOSFETs having differently processed SiON and HKMG gate insulators, in planar SiGe MOSFETs and also in Si FinFETs.  The contents also include a detailed investigation of the gate insulator process dependence of BTI in differently processed SiON and HKMG MOSFETs. The book then goes on to discuss Reaction-Diffusion (RD) model to estimate generation of new traps for DC and AC NBTI stress, and Transient Trap Occupancy Model (TTOM) to estimate charge occupancy of generated traps and their contribution to BTI degradation. Finally, a comprehensive NBTI modeling framework including TTOM enabled RD model and hole trapping to predict time evolution of BTI degradation and recovery during and after DC stress for different stress and recovery biases and temperature, during consecutive arbitrary stress and recovery cycles, and during AC stress at different frequency and duty cycle. The contents of this book should prove useful to academia and professionals alike

A study of NBTI in HfSiON/TiN p-MOSFETs using ultra-fast on-the-fly (UF-OTF) IDLIN technique

Negative Bias Temperature Instability (NBTI) is studied in HfSiON/TiN p-MOSFETs having thin (2 nm) and thick (3 nm) HfSiON layer on top of 1 nm SiO₂ interfacial layer. By using ultra fast on the fly IDLIN technique, the impact of stress temperature (T) and oxide field (EOX) on NBTI time evolution is studied. The thickness of the HfSiON layer is shown to have negligible impact on time, T and EOX dependence of NBTI. The impact of time-zero (t0) delay on power law time exponent (n), EOX acceleration (Γ) of degradation and EOX acceleration (β) of time to fail (ttF) is also studied. The t0 does not impact Γ but strongly impacts n, β and hence extracted safe operating voltage (VGSAFE)

A novel gate-assisted reverse-read scheme to control bit coupling and read disturb for multibit/cell operation in deeply scaled split-gate SONOS flash EEPROM cells

A dual-node split-gate silicon-oxide-nitride-oxide-silicon cell with a novel read scheme is proposed for 2-bit/cell operation. Using suitable gate screening bias in reverse read, bit coupling can be reduced, even when low read VD is used to keep read disturb under control. The proposed read scheme maintains the memory window for dual-bit/cell operation for deeply scaled cells. Two-dimensional process, device, and Monte Carlo simulations are extensively used to design and understand cell operation

Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation

Recent advances in experimental techniques (on-the-fly and ultrafast techniques) allow measurement of threshold voltage degradation due to negative-bias temperature instability (NBTI) over many decades in timescale. Such measurements over wider temperature range (−25 ◦C to 145 ◦C), film thicknesses (1.2–2.2 nm of effective oxide thickness), and processing conditions (variation of nitrogen within gate dielectric) provide an excellent framework for a theoretical analysis of NBTI degradation. In this paper, we analyze these experiments to refine the existing theory of NBTI to 1) explore the mechanics of time transients of NBTI over many orders of magnitude in time; 2) establish field dependence of interface trap generation to resolve questions regarding the appropriateness of power law versus exponential projection of lifetimes; 3) ascertain the relative contributions to NBTI from interface traps versus hole trapping as a function of processing conditions; and 4) briefly discuss relaxation dynamics for fast-transient NBTI recovery that involves interface traps and trapped holes