N-way Digitally Driven Doherty Power Amplifier Design and Analysis for Ku band Applications

With an increasing interest in backwards compatibility for existing satellites and the emerging satellite markets, wireless transceivers at Ku band are increasing in popularity. This paper presents the design of a four-way digitally driven Doherty amplifier, aimed at applications in Ku-band. Single tone measurements indicate a maximum drain efficiency of 53.4% at a maximum of 19.2 dBm output power. The final output power can readily be adjusted by changing the biasing in each stage accordingly. The N-way Doherty power amplifier was tested with an 800 MHz bandwidth, 64 QAM test signal aimed for future communication signal standards. An analysis of this configuration has also been performed for 2-way, 3-way and 4-way architectures

Behavioural Models for Distributed Arrays of High Performance Doherty Power Amplifiers

Behavioral models are intended as high level mathematical descriptions which require less computational effort to simulate behavior compared to physical or circuit level equivalent models. When designed and dimensioned properly they are well suited to concise characterization of power amplifiers under different operating conditions. In this paper we compare the relative performance of several behavioral models for modelling an asymmetric Doherty power amplifier for their use in distributed arrays

Digital Pre-distortion Implemented Using FPGA

Massive-MIMO and beamforming techniques have long been proposed as a means of increasing cellular network capacity and improving signal to interference ratio performance. The implementation of such systems requires a large number of signal transmission paths. To realize this, a distributed array of power amplifiers (PAs) is likely to be needed. These PAs will possess similar, but unique, characteristics which will alter over time independently due to temperature drift and component ageing. In order to operate all PAs in both a linear and efficient fashion a linearisation technique, such as Digital Pre-Distortion (DPD), must be used. DPD algorithms benefit from reconfigurability, low latency and power efficiency, all traits associated with Field Programmable Gate Arrays (FPGAs). This demonstration shows how an FPGA, specifically a ZYNQ System on a Chip (SoC), can be used in tandem with a transceiver board, the FMCOMMS2, to implement a DPD system

Wideband Interleaved Vector Modulators for 5G Wireless Communications

Next generation wireless communication systems such as fifth generation mobile communications and high throughput satellites have promised a step increase in the rate at which digital data can be transmitted. This requires wideband modulators consisting of high speed digital to analogue converters and RF upconverters to generate the wideband signal of interest. In this paper we demonstrate a scheme to generate a wide bandwidth modulated signal by bandwidth interleaving multiple modulators of narrower bandwidths. The proposed scheme is experimentally validated with measured results on an 8PSK signals of symbol rate 80 MSPS with modulation characteristics in accordance with DVB-S2 standard

A Novel Physical Layer Encryption Scheme to Counter Eavesdroppers in Wireless Communications

Modern wireless communication systems employ wideband modulated RF carriers to communicate the data of interest between the nodes in the network. The security of communications has been conventionally addressed in the data link layers through scrambling and data encryption schemes. These schemes however do not secure the air interface parameters such as modulation scheme and leave them susceptible to eavesdropping and interception by man-in-the-middle platforms. Physical layer security schemes such as directional modulation, DFT S OFDM and RF fingerprinting have been proposed. In this paper, we propose a novel physical layer encryption scheme based on the spectral profile of the intended modulated signal through deliberately introduced constellation distortion to conceal the modulation scheme. The scheme uses a dispersive filter in the modulator with unique group delay profiles unknown to the eavesdropper. The appropriate inverse filter is employed in the authorized receivers to recover the original modulated basebands for demodulation

Analog and Digital Co-design Methods for Future Wireless Transmitters

Increasing demand to provide higher data rates with spectral purity sets high standards for future mobile communication systems. Future wireless communication transmitters are challenged to improve their performance with reduced power consumption. Work performed in this thesis aims at improving several key areas of a wireless transmitter architecture to be more efficient and reliant on their power consumption. A novel calibration technique based on constellation mapping of a quadrature amplitude modulated (QAM) signal is proposed to alleviate the analog impairments within a wireless transmitter at system level. This technique facilitates the mixed-signal approach towards building efficient, linear transmitters. A primary front-end component of a wireless transmitter is the Power Amplifier (PA). Advanced architectures for PAs with improved power efficiency need to be explored for these future wireless communication systems. Ameliorations made towards improving the hardware structure in literature provides a variety of advanced power amplifier architectures. In analyzing the needs for the future mobile communication standards, and the complex nature of the signals involved, the Doherty power amplifier (DPA) architecture has indicated promise over the years. In this work, further improvements have been made on existing state-of-the-art Doherty PA architectures to aid wider-bandwidth operation to transmit at higher data rates. A distributed structure of four-way digitally controlled inputs has been suggested and its operation was tested at Ku-band frequency range. Furthermore, in simulating advanced PA architectures such as mentioned above, the time taken to perform a single simulation for a PA is significant. As a result, in-order to perform a system level simulation of a transmitter with several PA’s and other components will be even more apparent and less convenient. Therefore, for futuristic applications such as distributed arrays, a method of behavioral modeling of a fabricated asymmetrical DPA is suggested and tested

Analog and Digital Co-design Methods for Future Wireless Transmitters

Increasing demand to provide higher data rates with spectral purity sets high standards for future mobile communication systems. Future wireless communication transmitters are challenged to improve their performance with reduced power consumption. Work performed in this thesis aims at improving several key areas of a wireless transmitter architecture to be more efficient and reliant on their power consumption. A novel calibration technique based on constellation mapping of a quadrature amplitude modulated (QAM) signal is proposed to alleviate the analog impairments within a wireless transmitter at system level. This technique facilitates the mixed-signal approach towards building efficient, linear transmitters. A primary front-end component of a wireless transmitter is the Power Amplifier (PA). Advanced architectures for PAs with improved power efficiency need to be explored for these future wireless communication systems. Ameliorations made towards improving the hardware structure in literature provides a variety of advanced power amplifier architectures. In analyzing the needs for the future mobile communication standards, and the complex nature of the signals involved, the Doherty power amplifier (DPA) architecture has indicated promise over the years. In this work, further improvements have been made on existing state-of-the-art Doherty PA architectures to aid wider-bandwidth operation to transmit at higher data rates. A distributed structure of four-way digitally controlled inputs has been suggested and its operation was tested at Ku-band frequency range. Furthermore, in simulating advanced PA architectures such as mentioned above, the time taken to perform a single simulation for a PA is significant. As a result, in-order to perform a system level simulation of a transmitter with several PA’s and other components will be even more apparent and less convenient. Therefore, for futuristic applications such as distributed arrays, a method of behavioral modeling of a fabricated asymmetrical DPA is suggested and tested

Analog and Digital Co-design Methods for Future Wireless Transmitters

Increasing demand to provide higher data rates with spectral purity sets high standards for future mobile communication systems. Future wireless communication transmitters are challenged to improve their performance with reduced power consumption. Work performed in this thesis aims at improving several key areas of a wireless transmitter architecture to be more efficient and reliant on their power consumption. A novel calibration technique based on constellation mapping of a quadrature amplitude modulated (QAM) signal is proposed to alleviate the analog impairments within a wireless transmitter at system level. This technique facilitates the mixed-signal approach towards building efficient, linear transmitters. A primary front-end component of a wireless transmitter is the Power Amplifier (PA). Advanced architectures for PAs with improved power efficiency need to be explored for these future wireless communication systems. Ameliorations made towards improving the hardware structure in literature provides a variety of advanced power amplifier architectures. In analyzing the needs for the future mobile communication standards, and the complex nature of the signals involved, the Doherty power amplifier (DPA) architecture has indicated promise over the years. In this work, further improvements have been made on existing state-of-the-art Doherty PA architectures to aid wider-bandwidth operation to transmit at higher data rates. A distributed structure of four-way digitally controlled inputs has been suggested and its operation was tested at Ku-band frequency range. Furthermore, in simulating advanced PA architectures such as mentioned above, the time taken to perform a single simulation for a PA is significant. As a result, in-order to perform a system level simulation of a transmitter with several PA’s and other components will be even more apparent and less convenient. Therefore, for futuristic applications such as distributed arrays, a method of behavioral modeling of a fabricated asymmetrical DPA is suggested and tested

N-way Digitally Driven Doherty Power Amplifier Design and Analysis for Ku band Applications

With an increasing interest in backwards compatibility for existing satellites and the emerging satellite markets, wireless transceivers at Ku band are increasing in popularity. This paper presents the design of a four-way digitally driven Doherty amplifier, aimed at applications in Ku-band. Single tone measurements indicate a maximum drain efficiency of 53.4% at a maximum of 19.2 dBm output power. The final output power can readily be adjusted by changing the biasing in each stage accordingly. The N-way Doherty power amplifier was tested with an 800 MHz bandwidth, 64 QAM test signal aimed for future communication signal standards. An analysis of this configuration has also been performed for 2-way, 3-way and 4-way architectures

N-way Digitally Driven Doherty Power Amplifier Design and Analysis for Ku band Applications

With an increasing interest in backwards compatibility for existing satellites and the emerging satellite markets, wireless transceivers at Ku band are increasing in popularity. This paper presents the design of a four-way digitally driven Doherty amplifier, aimed at applications in Ku-band. Single tone measurements indicate a maximum drain efficiency of 53.4% at a maximum of 19.2 dBm output power. The final output power can readily be adjusted by changing the biasing in each stage accordingly. The N-way Doherty power amplifier was tested with an 800 MHz bandwidth, 64 QAM test signal aimed for future communication signal standards. An analysis of this configuration has also been performed for 2-way, 3-way and 4-way architectures