Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 $\mu$m$^2$ pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80$^\circ$) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.Comment: Nuclear Instruments and Methods A, in pres

Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

The ATLAS experiment will undergo around the year 2025 a replacement of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) with a new 5-layer pixel system. Thin planar pixel sensors are promising candidates to instrument the innermost region of the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. The sensors of 50-150 $\mu$m thickness, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests. In particular active edge sensors have been investigated. The performance of two different versions of edge designs are compared: the first with a bias ring, and the second one where only a floating guard ring has been implemented. The hit efficiency at the edge has also been studied after irradiation at a fluence of $10^{15}$ \neqcm. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 $\mu$m$^2$ pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angles with respect to the short pixel direction. Results on the hit efficiency in this configuration are discussed for different sensor thicknesses

Performance of irradiated thin n-in-p planar pixel sensors for the ATLAS Inner Tracker upgrade

The ATLAS collaboration will replace its tracking detector with new all silicon pixel and strip systems. This will allow to cope with the higher radiation and occupancy levels expected after the 5-fold increase in the luminosity of the LHC accelerator complex (HL-LHC). In the new tracking detector (ITk) pixel modules with increased granularity will implement to maintain the occupancy with a higher track density. In addition, both sensors and read-out chips composing the hybrid modules will be produced employing more radiation hard technologies with respect to the present pixel detector. Due to their outstanding performance in terms of radiation hardness, thin n-in-p sensors are promising candidates to instrument a section of the new pixel system. Recently produced and developed sensors of new designs will be presented. To test the sensors before interconnection to chips, a punch-through biasing structure has been implemented. Its design has been optimized to decrease the possible tracking efficiency losses observed. After irradiation, they were caused by the punch-through biasing structure. A sensor compatible with the ATLAS FE-I4 chip with a pixel size of 50x250 $\mathrm{\mu}$m$^{2}$, subdivided into smaller pixel implants of 30x30 $\mathrm{\mu}$m$^{2}$ size was designed to investigate the performance of the 50x50 $\mathrm{\mu}$m$^{2}$ pixel cells foreseen for the HL-LHC. Results on sensor performance of 50x250 and 50x50 $\mathrm{\mu}$m$^{2}$ pixel cells in terms of efficiency, charge collection and electric field properties are obtained with beam tests and the Transient Current Technique

Development of a timing chip prototype in 110 nm CMOS technology

We present a readout chip prototype for future pixel detectors with timing capabilities. The prototype is intended for characterizing 4D pixel arrays with a pixel size of $100\times100~\mu \text{m}^2$, where the sensors are Low Gain Avalanche Diodes (LGADs). The long-term focus is towards a possible replacement of disks in the extended forward pixel system (TEPX) of the CMS experiment during the High Luminosity LHC (HL-LHC). The requirements for this ASIC are the incorporation of a Time to Digital Converter (TDC) within each pixel, low power consumption, and radiation tolerance up to $5\times10^{15}~n_\text{eq}\text{~cm}^{-2}$ to withstand the radiation levels in the innermost detector modules for $3000 \text{fb}^{-1}$ of the HL-LHC (in the TEPX). A prototype has been designed and produced in 110~nm CMOS technology at LFoundry and UMC with different versions of TDC structures, together with a front end circuitry to interface with the sensors. The design of the TDC will be discussed, with the test set-up for the measurements, and the first results comparing the performance of the different structures

Characterization of timing and spacial resolution of novel TI-LGAD structures before and after irradiation

The characterization of spacial and timing resolution of the novel Trench Isolated LGAD (TI-LGAD) technology is presented. This technology has been developed at FBK with the goal of achieving 4D pixels, where an accurate position resolution is combined in a single device with the precise timing determination for Minimum Ionizing Particles (MIPs). In the TI-LGAD technology, the pixelated LGAD pads are separated by physical trenches etched in the silicon. This technology can reduce the interpixel dead area, mitigating the fill factor problem. The TI-RD50 production studied in this work is the first one of pixelated TI-LGADs. The characterization was performed using a scanning TCT setup with an infrared laser and a $^{90}$Sr source setup

Characterization of passive CMOS sensors with RD53A pixel modules

Both the current upgrades to accelerator-based HEP detectors (e.g. ATLAS, CMS) and also future projects (e.g. CEPC, FCC) feature large-area silicon-based tracking detectors. We are investigating the feasibility of using CMOS foundries to fabricate silicon radiation detectors, both for pixels and for large-area strip sensors. A successful proof of concept would open the market potential of CMOS foundries to the HEP community, which would be most beneficial in terms of availability, throughput and cost. In addition, the availability of multi-layer routing of signals will provide the freedom to optimize the sensor geometry and the performance, with biasing structures implemented in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150nm CMOS process. This presentation will focus on the characterization of pixel modules, studying the performance in terms of charge collection, position resolution and hit efficiency with measurements performed in the laboratory and with beam tests. We will report on the investigation of RD53A modules with 25x100 μm$^{2}$ cell geometry

Characterization of passive CMOS sensors with RD53A pixel modules

Both the current upgrades to accelerator-based HEP detectors (e.g. ATLAS, CMS) and also future projects (e.g. CEPC, FCC) feature large-area silicon-based tracking detectors. We are investigating the feasibility of using CMOS foundries to fabricate silicon radiation detectors, both for pixels and for large-area strip sensors. A successful proof of concept would open the market potential of CMOS foundries to the HEP community, which would be most beneficial in terms of availability, throughput and cost. In addition, the availability of multi-layer routing of signals will provide the freedom to optimize the sensor geometry and the performance, with biasing structures implemented in poly-silicon layers and MIM-capacitors allowing for AC coupling. A prototyping production of strip test structures and RD53A compatible pixel sensors was recently completed at LFoundry in a 150nm CMOS process. This presentation will focus on the characterization of pixel modules, studying the performance in terms of charge collection, position resolution and hit efficiency with measurements performed in the laboratory and with beam tests. We will report on the investigation of RD53A modules with 25x100 μm$^{2}$ cell geometry