Catastrophic degradation of the interface of epitaxial silicon carbide on silicon at high temperatures

© 2016 Author(s). Epitaxial cubic silicon carbide on silicon is of high potential technological relevance for the integration of a wide range of applications and materials with silicon technologies, such as micro electro mechanical systems, wide-bandgap electronics, and graphene. The hetero-epitaxial system engenders mechanical stresses at least up to a GPa, pressures making it extremely challenging to maintain the integrity of the silicon carbide/silicon interface. In this work, we investigate the stability of said interface and we find that high temperature annealing leads to a loss of integrity. High-resolution transmission electron microscopy analysis shows a morphologically degraded SiC/Si interface, while mechanical stress measurements indicate considerable relaxation of the interfacial stress. From an electrical point of view, the diode behaviour of the initial p-Si/n-SiC junction is catastrophically lost due to considerable inter-diffusion of atoms and charges across the interface upon annealing. Temperature dependent transport measurements confirm a severe electrical shorting of the epitaxial silicon carbide to the underlying substrate, indicating vast predominance of the silicon carriers in lateral transport above 25 K. This finding has crucial consequences on the integration of epitaxial silicon carbide on silicon and its potential applications

Nanoindentation based fracture studies of ITO coating.

Nano-scale load (P) dependency of fracture toughness (K1C) of indium tin oxide (ITO) coating on silicon (Si) substrate is evaluated by nanoindentation based direct and energy methods. A Berkovich triangular diamond nanoindenter is used with nine different P values e.g., 10, 15, 20, 30, 40, 50, 100, 150 and 200 mN. Extensive utilization of both optical microscopy (OM) and field emission scanning electron microscopy (FESEM) techniques reveal that up to P ≤ 40 mN only the sharp radial cracks form from three corners of the nanoindent. However, for P > 40 mN, multiple cracks occur over and above the radial cracks. Finally, at P: 150–200 mN coating gets chipped off from the substrate. The K1C values of the ITO coating are calculated on the basis of both the conventional radial crack length measurement based method and the strain energy release based method. The K1C values are strongly sensitive to variations in P. Further, the strain energy method results in higher magnitudes of the K1C values

Nanoindentation response of ITO film

We report nanoindentation response of indium tin oxide (ITO) film deposited by reactive direct current (DC) magnetron sputtering. The phase pure ITO film showed dense and needle-like nanostructure. Detailed mechanical characterization of ITO film was carried out by the nanoindentation technique. The average nanohardness and elastic modulus were evaluated as about 17.5 GPa and 189 GPa, respectively. Comparatively higher nanohardness and modulus values were found in the present work, which is possibly linked with the dense nanostructure of the ITO film. Further, fracture toughness was measured as ~0.56 MPa.m0.5. The corresponding projected area of indentation, elastic energy and plastic energy were also reported

Reversible phase transition in vanadium oxide films sputtered on metal substrates

Vanadium oxide films, deposited on aluminium (Al), titanium (Ti) and tantalum (Ta) metal substrates by pulsed RF magnetron sputtering at a working pressure of 1.5 x10−2 mbar at room temperature are found to display mixed crystalline vanadium oxide phases viz., VO2, V2O3, V2O5. The films have been characterized by field-emission scanning electron microscopy, X-ray diffraction, differential scanning calorimetry (DSC) and X-ray photoelectron spectroscopy, and their thermo-optical and electrical properties have been investigated. Studies of the deposited films by DSC have revealed a reversible-phase transition found in the temperature range of 45–49 °C

P-Type Epitaxial Graphene on Cubic Silicon Carbide on Silicon for Integrated Silicon Technologies

Copyright © 2019 American Chemical Society. The synthesis of graphene on cubic silicon carbide on silicon pseudosubstrates draws enormous interest due to the potential integration of the 2D material with the well-established silicon technology and processing. However, the control of transport properties over large scales on this platform, essential for integrated electronics and photonics applications, has lagged behind so far, due to limitations such as 3C-SiC/Si interface instability and nonuniform graphene coverage. We address these issues by obtaining an epitaxial graphene (EG) onto 3C-SiC on a highly resistive silicon substrate using an alloy-mediated, solid-source graphene synthesis. We report the transport properties of EG grown over large areas directly on 3C-SiC(100) and 3C-SiC(111) substrates, and we present the corresponding physical models. We observe that the carrier transport of EG/3C-SiC is dominated by the graphene-substrate interaction rather than the EG grain size, sharing the same conductivity and same inverse power law as EG on 4H- or 6H-SiC(0001) substrates - although the grain sizes for the latter are vastly different. In addition, we show that the induced oxidation/silicates at the EG/3C-SiC interface generate a p-type charge in this graphene, particularly high for the EG/3C-SiC(001). When silicates are at the interface, the presence of a buffer layer in the EG/3C-SiC(111) system is found to reduce somewhat the charge transfer. This work also indicates that a renewed focus on the understanding and engineering of the EG interfaces could very well enable the long sought-after graphene-based electronics and photonics integrated on silicon