17 GHz Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 mum SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 mus, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25-30 dB into a 50 Omega load at 10 MHz IF, and noise figure is 12 plusmn0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is -37 dBm and IIP3 is -25 dBm. The maximum saturated output power from the on-chip transmit amplifier is -1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 muA

A 40 GHz, broadband, highly linear amplifier, employing T-coil bandwith extension technique

This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply

A Ka band, static, MCML frequency divider, in standard 90nm-CMOS LP for 60 GHz applications

This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset from the carrier