Subthreshold FIR Filter Architecture for Ultra Low Power Applications

Subthreshold design has been proposed as an effective technique for designing signal processing circuits needed in wireless sensor nodes powered by sources with limited energy. In this paper we propose a subthreshold FIR architecture which brings the benefits of reducedleakage energy, reduced minimum energy point, reduced operating voltage and increased operating frequency when compared with recently reported subthreshold designs. We shall demonstrate this through the design of a 9-tap FIR filter operating at 220mV with operational frequency of 126kHz/sample consuming 168.3nW or 1.33pJoules/sample. Furthermore, the area overhead of the proposed method is less than that of the transverse structure often employed in subthreshold filter designs. For example, a 9-tap filter based on transverse structure has 5X higher area than the filter designed using our proposed method

Viterbi decoding on a coprocessor architecture with vector parallelism

A programmable coprocessor architecture combining VLIW and vector parallelism has been introduced (van Berkel, K. et al., Proc. World Wireless Congress, 2003). We present the mapping of the Viterbi decoding algorithm on this architecture. Initially, algorithm analysis and vectorizing transformations are discussed. The resulting vectorized algorithm is used for defining two generic vector instructions for Viterbi decoding. These are the 'add-compare-select' (ACS) and Manhattan distance (MANH) instructions. The design of these instructions is presented and their genericity is demonstrated by discussing how various Viterbi decoder instances (such as M'ary Viterbi and Viterbi decoding for blind. transport format detection) can be implemented using CVP (co-vector processor) Viterbi instructions. Finally, the throughput estimations of two binary Viterbi decoder implementations (UMTS and GSM) are benchmarked against a number of existing processors. The results present a higher throughput than comparable architectures, demonstrating that a good tradeoff has been achieved between instruction set flexibility and decoding throughput