Mixed-signal circuits and boards for high safety applications

A design methodology for analogue on-line test is presented by means of a real circuit implementation. The test strategy is based on monitoring via a very small analogue checker the inputs of all operational ampliers of a fully di erential circuit. The self-checking properties of the functional circuit are evaluated for a hard/soft fault model. Since the analogue checker outputs a double-rail error indication, the compatibility with digital checkers is ensured and the design of self-checking mixed-signal circuits becomes very simple. The mixed-signal approach is extended toboards through the IEEE Std. 1149.1 digital test bus and a layout rule to avoid interconnect di erential shorts.

Diversity TMR: Proof of Concept in a Mixed-Signal Case

Abstract-In this paper a design diversity fault tolerance technique is applied to a mixed-signal (MS) system. Three different implementations of a second order low-pass filter (which perform the same transfer function) associated to a majority voter are used to build the TMR scheme. The whole system is prototyped by using a programmable mixed-signal device. Some functional faults are injected into the circuit blocks and practical measurements are made on the prototyped system. Results show that the design diversity TMR is a feasible technique that can increase reliability of some classes of state-ofart MS circuits

An automated verification process based on scan techniques

Matching the results achieved during circuit simulation with those extracted from circuit operation is a common verification process. A large number of current verification techniques use the input / output vectors produced during functional simulation as the test vectors applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes a solution for verifying digital designs implemented in commercially available CLPDs. All internal flip-flops are included in a scan chain accessible through the BST infrastructure (through a user-defined optional instruction), while the BS cells are used to apply the input test vectors and capture the circuit responses. These BS cells can either belong to the device-under-test or to other devices, in the former case through the optional INTEST instruction and in the latter through the mandatory EXTEST instruction. To speed up the verification process, the test program is automatically generated from information that encompasses the design and development phase

Design of systems on a chip : introduction

This introductory chapter briefly discusses the impacts into chip design and production of integrating highly complex electronic systems as systems on a chip. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. The contents of the book are shortly presented in the sequel, comprising contributions on three different, but complementary axes: core design, computer-aided design tools and test method

From digital to analog self-checking circuits

International audienc

On-Line Testing of Opamp Circuits Using Built-In Detector Observer

International audienc

Design of Self-Checking and Fail-Safe Integrated Circuits

International audienc

Design of Self-Checking Integrated Circuits and Boards

International audienc

An approach to the on-line testing of operational amplifiers

A new approach for the on-line testing of operational amplifiers embedded into analog and mixed-signal circuits is presented in this paper. A built-in detector is used for providing an on-line test signal, which is suitable for concurrent error detection in operational amplifiers. The fault detection strategy is based on monitoring via an analog checker the normal output/input and the on-line signal of operational amplifiers. In this context, the circuitry associated with a self-checking operational amplifier is presented. In order to evaluate the fault coverage and the performance degradation in the resulting operational amplifier, extensive simulations are performed considering catastrophic faults