Shielded Ohmic Contact (ShOC) Rectifier: A New Metal-Semiconductor Device with Excellent Forward and Reverse Characteristics

We report a new structure, called the Shielded Ohmic Contact (ShOC) rectifier which utilizes trenches filled with a high barrier metal to shield an Ohmic contact during the reverse bias. When the device is forward biased, the Ohmic contact conducts with a low forward drop. However, when reverse biased, the Ohmic contact is completely shielded by the high barrier Schottky contact resulting in a low reverse leakage current. Two dimensional numerical simulation is used to evaluate and explain the superior performance of the proposed ShOC rectifier.Comment: http://web.iitd.ac.in/~mamidala

New Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET): Design and Analysis using Two-dimensional Simulation

A new Schottky-gate Bipolar Mode Field Effect Transistor (SBMFET) is proposed and verified by two-dimensional simulation. Unlike in the case of conventional BMFET, which uses deep diffused p+-regions as the gate, the proposed device uses the Schottky gate formed on the silicon planar surface for injecting minority carriers into the drift region. The SBMFET is demonstrated to have improved current gain, identical breakdown voltage and ON-voltage drop when compared to the conventional BMFET. Since the fabrication of the SBMFET is much simpler and obliterates the need for deep thermal diffusion of P+-gates, the SBMFET is expected to be of great practical importance in medium-power high-current switching applications.Comment: Journal Pape

Bipolar Charge Plasma Transistor: A Novel Three Terminal Device

A distinctive approach for forming a lateral Bipolar Charge Plasma Transistor (BCPT) is explored using 2-D simulations. Different metal work-function electrodes are used to induce n- and p-type charge plasma layers on undoped SOI to form the emitter, base and collector regions of a lateral NPN transistor. Electrical characteristics of the proposed device are simulated and compared with that of a conventionally doped lateral bipolar junction transistor with identical dimensions. Our simulation results demonstrate that the BCPT concept will help us realize a superior bipolar transistor in terms of a high current gain compared to a conventional BJT. This BCPT concept is suitable in overcoming doping issues such as dopant activation and high-thermal budgets which are serious issues in ultra thin SOI structures

New Silicon Carbide (SiC) Hetero-Junction Darlington Transistor

Basic SiC bipolar transistors have been studied in the past for their applications where high power or high temperature operation is required. However since the current gain in SiC bipolar transistors is very low and therefore, a large base drive is required in high current applications. Therefore, it is important to enhance the current gain of SiC bipolar transistors. Using two dimensional mixed mode device and circuit simulation, for the first time, we report a new Darlington transistor formed using two polytypes 3C-SiC and 4H-SiC having a very high current gain as a result of the heterojunction formation between the emitter and the base of transistor. The reasons for the improved performance are analyzed.Comment: http://web.iitd.ac.in/~mamidala

Estimation and Compensation of Process Induced Variations in Nanoscale Tunnel Field Effect Transistors (TFETs) for Improved Reliability

Tunnel Field Effect Transistors (TFET) have extremely low leakage current, exhibit excellent subthreshold swing and are less susceptible to short channel effects. However, TFETs do face certain special challenges, particularly with respect to the process induced variations in (i) the channel length and (ii) the thickness of the silicon thin-film and the gate oxide. This paper, for the first time, studies the impact of the above process variations on the electrical characteristics of a Double Gate Tunnel Field Effect Transistor (DGTFET). Using two dimensional device simulations, we propose the Strained Double Gate Tunnel Field Effect Transistor (SDGTFET) with high-k gate dielectric as a possible solution for effectively compensating the process induced variations in the on-current, threshold voltage and subthreshold-swing improving the reliability of the DGTFET.Comment: Journal Pape

Schottky Collector Bipolar Transistor without Impurity Doped Emitter and Base: Design and Performance

In this paper, we report an alternative approach of implementing a Schottky collector bipolar transistor without doping the ultrathin SOI film. Using different metal work function electrodes, the electrons and holes are induced in an intrinsic silicon film to create the n emitter and the p base regions, respectively. Using two-dimensional device simulation, the performance of the proposed device has been evaluated. Our results demonstrate that the charge plasma based bipolar transistor with Schottky collector exhibits a high current gain and a better cut-off frequency compared to its conventional counterpart

Dielectric-Modulated Impact-Ionization MOS (DIMOS) Transistor as a Label-free Biosensor

In this letter, we propose a dielectric-modulated Impact-Ionization MOS (DIMOS) transistor based sensor for application in label-free detection of biomolecules. Numerous reports exist on the experimental demonstration of nanogap-embedded FET-based biosensors, but an I-MOS based biosensor has not been reported previously. The concept of a dielectric-modulated I-MOS based biosensor is presented in this letter based on TCAD simulation study. The results indicate a high sensitivity to the presence of biomolecules even at small channel lengths. In addition, a low variability of the sensitivity to the charges on the biomolecule is observed. The high sensitivity, dominance of dielectric-modulation effects and operation at even small channel lengths makes the DIMOS biosensor a promising alternative for CMOS-based sensor applications

Compact Analytical Model of Dual Material Gate Tunneling Field Effect Transistor using Interband Tunneling and Channel Transport

In this paper we have developed a two dimensional (2D) analytical model for surface potential and drain current for a long channel Dual Material Gate (DMG) Silicon-on-Insulator (SOI) Tunneling Field Effect Transistor (TFET). This model includes the effect of drain voltage, gate metal work function, oxide thickness and silicon film thickness, without assuming a fully depleted channel. The proposed model also includes the effect of charge accumulation at the interface of the two gates and the variation in the tunneling volume with the applied gate voltage. The accuracy of the model is tested using two-dimensional numerical simulations. In comparison to the conventional TFET, the proposed model predicts that a DMGTFET provides a higher ON-state current (ION), a better ON-state to OFF-state current (ION/IOFF) ratio and a better sub-threshold slope (SS)

A New Strained-Silicon Channel Trench-gate Power MOSFET: Design and Analysis

In this paper, we propose a new trench power MOSFET with strained Si channel that provides lower on resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si1-xGex body with a compositionally graded Si1-xGex buffer in the drift region enables us to create strain in the channel along with graded strain in the accumulation region. As a result, the proposed structure exhibits 40% enhancement in current drivability, 28% reduction in the on-resistance and 72% improvement in peak transconductance at the cost of only 12% reduction in the breakdown voltage when compared to the conventional trench gate MOSFET. Furthermore, the graded strained accumulation region supports the confinement of carriers near the trench sidewalls improving the field distribution in the mesa structure useful for a better damage immunity during inductive switching.Comment: http://web.iitd.ac.in/~mamidal

A New High Voltage 4H-SiC Lateral Dual Sidewall Schottky (LDSS) Rectifier: Theoretical Investigation and Analysis

In this paper, we report a new 4H-SiC Lateral Dual Sidewall Schottky (LDSS) rectifier on a highly doped drift layer consisting of a high-barrier sidewall Schottky contact on top of the low-barrier Schottky contact. Using two-dimensional device simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the compatible Lateral Conventional Schottky (LCS) and Lateral Trench Sidewall Schottky (LTSS) rectifiers on 4H-SiC. From our simulation results, it is observed that the proposed LDSS rectifier acts as a low-barrier LTSS rectifier under forward bias conditions and as a high-barrier LTSS rectifier under reverse bias conditions making it an ideal rectifier. The LDSS rectifier exhibits an on/off current ratio (at 1 V / -500 V) of 5.5x10e7 for an epitaxial layer doping of 1x10e17 /cm^3. Further, the proposed LDSS structure exhibits a very sharp breakdown similar to that of a PiN diode in spite of using only Schottky junctions in the structure. We have analyzed the reasons for the improved performance of the LDSS.Comment: http://web.iitd.ac.in/~mamidala