9 research outputs found
High-resolution FPGA-based image processing
W publikacji przedstawiono zarys problematyki akwizycji i transmisji obrazu wysokiej rozdzielczo艣ci. Om贸wiono architektur臋 kompleksowych system贸w przetwarzania obraz贸w w kontek艣cie implementacji w uk艂adach FPGA. Poruszono tematyk臋 architektury toru wizyjnego. Pokazano zaproponowany i zestawione stanowisko do analizy obraz贸w wysokiej rozdzielczo艣ci. Pokazano osi膮gni臋te rezultaty, wskazuj膮c na wysok膮, mo偶liw膮 do osi膮gni臋cia wydajno艣膰 uk艂adu FPGA jako procesora wizyjnego.The paper presents an outline of HD image acquisition and transmis-sion. Attention is paid to the video signal of high bit rate, transmitted from the digital video camera as a data stream. Interfaces between digital video cameras and accelerators card for image processing are listed. The paper discusses the architecture of complex, image processing, reconfigurable, FPGA-based systems. The author draws attention to the changing nature of calculations during the transition from image processing to image analysis. There is proposed a strategy for integration in FPGA both pipelined MISD (Multiple Instruction Streams Single Data Stream) architecture and MIMD (Multiple Instruction Streams Multiple Data Streams) parallel system for implementing calculations in a homogenous computing environment of FPGA resources. There is proposed a laboratory stand consisting of a set of devices for high-resolution image acquisition and processing using the Camera Link. There are given the experiment results. It should be noted that the actual bus throughput significantly differs from the maximum values defined in the specifications of the used standards. There are shown the limitations of communication interfaces used, whereas at the same time there is emphesized the high, achievable performance of the FPGA as a video processor
FPGA Imaging System In Biocybernetics Lab
W artykule przedstawiono tematyk臋 bada艅 naukowych dotycz膮cych implementacji system贸w obrazowych FPGA, prowadzonych w Laboratorium Biocybernetyki Katedry Automatyki AGH. Pokazano g艂贸wne kierunki bada艅 na 艣wiecie i dokonano przegl膮du literatury w zakresie implementacji przetwarzania i analizy obraz贸w w uk艂adach FPGA. Na tym tle pokazano prace wykonane w Laboratorium Biocybernetyki, wskazuj膮c na istotny aspekt energooszcz臋dno艣ci implementacji FPGA.The paper presents the research topics concerning the implementation of FPGA imaging systems, conducted at the Biocybernetics Laboratory of Department of Automatics AGH-University of Science and Technology. Shows the main directions of research in the world and an overview of the literature in the field of FPGA-based image processing and analysis. On this background showing the work done at the Biocybernetics Laboratory, pointing to an important aspect of energy efficiency at FPGA systems
Hardware implementation of the ViBe background subtraction method in FPGA
W artykule zaprezentowano implementacj臋 sprz臋tow膮 nowatorskiego algorytmu odejmowania t艂a ViBe (ang. VIsual Background Extractor) w uk艂adzie rekonfigurowalnym FPGA. Metoda ta opiera si臋 na odmiennej od dotychczas opisywanych i realizowanych koncepcji modelowania t艂a. W pracy dokonano oceny mo偶liwo艣ci przeniesienia algorytmu na platform臋 sprz臋tow膮, pokazano dwie modyfikacje, kt贸re pozwoli艂y poprawi膰 dzia艂anie metody oraz om贸wiono zrealizowany system sprz臋towy. Wed艂ug wiedzy autor贸w jest to pierwszy opis implementacji tego algorytmu w uk艂adzie FPGA.This paper presents a hardware implementation in the FPGA reconfigurable device of ViBe - a novel background subtraction algorithm. The method is based on a different, from those previously described and implemented, background modelling concept. It partly uses random numbers, which allowed us to significantly reduce the buffer size in relation to the standard methods like mean or median form a buffer. A detailed description of ViBe can be found in papers [6, 7, 8]. In this paper the role of background generation algorithms in image processing and analysis systems, with particular emphasis on hardware implementations is discussed (Section 1). The ViBe algorithm is described in Section 2. Then an analysis of the possibility of implementing ViBe in FPGA is presented (Section 3). Section 4 describes two proposed modifications: the use of the CIE Lab colour space and the enhanced flashing pixels detection method. Their desirability has been confirmed quantitatively using the "ChangeDetection" database [9]. A detailed description of the designed ViBe hardware module and image processing system is presented in Section 5. The scheme of the ViBe module is shown in Figure 5 and the whole system in Figure 4. Table 3 summarizes the hardware resource utilization. The proposed solution enables the detection of objects using the method ViBe and enables realtime processing of a colour 640 x 480 video stream at 60 frames per second. The obtained results confirm the high usefulness of FPGA in the implementation of advanced image processing and analysis algorithms
Implementacja detekcji obiekt贸w ruchomych w czasie rzeczywistym w systemach nadzoru wizyjnego z wykorzystaniem uk艂ad贸w FPGA
The article presents the concept of real-time implementation computing tasks in video surveillance systems. A pipeline implementation of a multimodal background generation algorithm for colour video stream and a moving objects segmentation based on brightness, colour and textural information in reconfigurable resources of FPGA device is described. System architecture, resource usage and segmentation results are presented.W artykule zaprezentowano koncepcj臋 implementacji zada艅 obliczeniowych wykorzystywanych w systemach nadzoru wizyjnego w czasie rzeczywistym. Opisano implementacj臋 wielomodalnej metody generacji t艂a dla sekwencji wideo zarejestrowanych w kolorze oraz segmentacj臋 obiekt贸w ruchomych z wykorzystaniem informacji o jasno艣ci, kolorze i teksturze w zasobach rekonfigurowalnych uk艂ad贸w FPGA. Zaprezentowano architektur臋 systemu, zu偶ycie zasob贸w i przyk艂adowe rezultaty segmentacji
A reconfigurable image acquisition and transmission module for video surveillance systems
W artykule opisano dzia艂aj膮cy w czasie rzeczywistym sprz臋towy modu艂 do odbioru strumienia wizyjnego z kamery HDMI, zmiany rozdzielczo艣ci obrazu oraz dalszej jego transmisji przy wykorzystaniu sieci Ethernet (1 Gbps). Aby mo偶liwe by艂o ograniczenie koszt贸w oraz wykorzystanie zaprezentowanego modu艂u w urz膮dzeniach wbudowanych, na 偶adnym etapie przetwarzania nie jest wykorzystywane buforowanie danych w zewn臋trznej pami臋ci. W ramach prac zosta艂o przebadane, jak parametry transmisji (rozmiar obrazu, maksymalny rozmiar pakiet贸w) wp艂ywaj膮 na jej przepustowo艣膰. Om贸wiono budow臋 ka偶dego z modu艂贸w, zu偶ycie zasob贸w FPGA ca艂ego systemu, rozpraszanie mocy, a tak偶e przyk艂adowe rezultaty dzia艂ania na p艂ycie ewaluacyjnej SP605 firmy Xilinx.Automated video surveillance systems are an important means of providing security. In projects such as SIMPOZ, INDECT or VIRAT the main tendency was to replace the human operator in a tedious task of video analysis. Because computer vision algorithms demand a lot of computational power, reconfigurable devices are often used for this type of applications. In the paper a module for video acquisition and transmission for a reconfigurable device is presented. It is the basic component of a reconfigurable based video surveillance system. An FMC card is used to allow FPGA to receive a video from the HDMI source (other FMC cards can be used if needed). In the next step, the image is streamed to module which scale it down. This operation is necessary to meet the bandwidth of transmission media and other modules processing capabilities. A hardware module provides Ethernet communication with 1 Gbps speed. Packet forming, checksum computation, ARP requests, IP and UDP protocols are realized in hardware using several finite state machines. The images or data obtained from analysis are transferred in UDP packets. The proposed system can process both grayscale and color images. The idea was verified using the Xilinx SP605 board with a low power Spartan 6 device
Parallel implementation of local thresholding in Mitrion-C
Mitrion-C based implementations of three image processing algorithms: a look-up table operation, simple local thresholding and Sauvola's local thresholding are described. Implementation results, performance of the design and FPGA logic utilization are discussed
A new architecture of the FPGA-based embedded vision system dedicated for smart cameras
W artykule przedstawiono przegl膮d wybranych metod pod艂膮czenia kamer z interfejsem cyfrowym do system贸w mikroprocesorowych lub rekonfigurowalnych, z podzia艂em na systemy z komputerem nadrz臋dnym oraz na tzw. smart camera. W drugim przypadku konieczne jest zadbanie o odpowiedni膮 architektur臋 odpowiedzialn膮 za przes艂anie zarejestrowanego obrazu do jednostek obliczeniowych. Zaprezentowano rozwijany system oparty o uk艂ad FPGA, o nowatorskiej architekturze, zawieraj膮cy dwa sensory CMOS i rozbudowany uk艂ad pami臋ci zewn臋trznych, mog膮cy s艂u偶y膰 do realizacji specyficznych zada艅 przetwarzania obraz贸w.Embedded vision systems are becoming more popular. A smart camera consists of an image sensor and a computing unit processing the image. Integration of many new functions in vision systems is now possible due to progress of resources of FPGA devices. A new vision system device presented in this paper is unique with regard to its architecture. The main goal during development of this smart camera was to provide it with a possibly large number of memory banks for storing image data, while keeping compact dimensions and low price. In the presented system there was chosen processing of monochromatic images, so significant reduction in the width of memory data buses was obtained. Thanks to that, up to eight fully independent memory banks was connected to the FPGA device. The second assumption was usage of static memories, which decided in favour of large functionality of the device, because very fast data transfer from random address location was then possible. This meets requirements of image processing algorithms, which is computing data in Region of Interest, for example
Reconfigurable video surveillance system for detecting intrusion into protected areas
W artykule opisano dzia艂aj膮cy w czasie rzeczywistym sprz臋towy system do detekcji naruszenia obszar贸w chronionych oparty o analiz臋 obrazu kolorowego o rozdzielczo艣ci 640 x 480 zaimplementowany w zasobach rekonfigurowalnych uk艂adu FPGA. Sk艂ada si臋 on z szeregu modu艂贸w: akwizycji obrazu, konwersji z przestrzeni barw RGB do CIE Lab, generacji t艂a z uwzgl臋dnieniem informacji o kraw臋dziach, odejmowania t艂a, binaryzacji warunkowej, filtru medianowego, dylatacji morfologicznej, indeksacji jednoprzebiegowej, analizy po艂o偶enia wykrytych obiekt贸w oraz wizualizacji wynik贸w. W pracy om贸wiono budow臋 ka偶dego z modu艂贸w, zu偶ycie zasob贸w FPGA, zu偶ycie mocy, a tak偶e przyk艂adowe rezultaty dzia艂ania.In the paper a hardware implementation of an algorithm for detection of intrusion into protected areas is presented. The system is composed of several functional modules: colour space conversion from RGB to CIE Lab, Sobel gradient calculation, background generation (running average algorithm), moving object segmentation, median filtering, morphological dilation, connected component labeling integrated with analysis of the detected objects (area and bounding box determination) and visualization of the detection results. The most important features of the proposed solution are: use of the CIE Lab colour space which allows improving segmentation results and reducing the noise introduced by shadows; advanced segmentation which is based on integration of luminance, chrominance and edge information and a thresholding scheme using two thresholds; use of a one-pass connected component labeling and analysis algorithm and its FPGA implementation. The use of a high-end Virtex 6 FPGA device allowed obtaining real-time performance in processing a 640 x 480 colour video stream. The proposed system was tested on several sequences. The obtained results show that it detects correctly the intrusion into protected zones. The module could be used in a smart-camera design, where the image processing and analysis is integrated with the imaging sensor and a surveillance system operator receives only information about intrusion detection