8,602 research outputs found

    FLARE: A design environment for FLASH-based space applications

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    Designing a mass-memory device (i.e., a solid-state recorder) is one of the typical issues of mission-critical space system applications. Flash-memories could be used for this goal: a huge number of parameters and trade-offs need to be explored. Flash-memories are nonvolatile, shock-resistant and power-economic, but in turn have different drawback: e.g., their cost is higher than normal hard disk and the number of erasure cycles is bounded. Moreover space environment presents various issues especially because of radiations: different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid-state recorder. No systematic approach has so far been proposed to consider them all as a whole: as a consequence a novel design environment currently under development is aimed at supporting the design of flash-based mass-memory device for space application

    Flash-memories in Space Applications: Trends and Challenges

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    Nowadays space applications are provided with a processing power absolutely overcoming the one available just a few years ago. Typical mission-critical space system applications include also the issue of solid-state recorder(s). Flash-memories are nonvolatile, shock-resistant and power-economic, but in turn have different drawbacks. A solid-state recorder for space applications should satisfy many different constraints especially because of the issues related to radiations: proper countermeasures are needed, together with EDAC and testing techniques in order to improve the dependability of the whole system. Different and quite often contrasting dimensions need to be explored during the design of a flash-memory based solid- state recorder. In particular, we shall explore the most important flash-memory design dimensions and trade-offs to tackle during the design of flash-based hard disks for space application

    Exploring Design Dimensions in Flash-based Mass-memory Devices

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    Mission-critical space system applications present several issues: a typical one is the design of a mass-memory device (i.e., a solid- state recorder). This goal could be accomplished by using flash- memories: the exploration of a huge number of parameters and trade-offs is needed. On the one hand flash-memories are nonvolatile, shock-resistant and power-economic, but on the other hand their cost is higher than normal hard disk, the number of erasure cycles is bounded and other different drawbacks have to be considered. In addition space environment presents various issues especially because of radiations: the design of a flash- memory based solid-state recorder implies the exploration of different and quite often contrasting dimensions. No systematic approach has so far been proposed to consider them all as a whole: as a consequence the design of flash-based mass-memory device for space applications is intended to be supported by a novel design environment currently under development and refinemen

    Design Issues and Challenges of File Systems for Flash Memories

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    This chapter discusses how to properly address the issues of using NAND flash memories as mass-memory devices from the native file system standpoint. We hope that the ideas and the solutions proposed in this chapter will be a valuable starting point for designers of NAND flash-based mass-memory devices

    Nociceptive-Evoked Potentials Are Sensitive to Behaviorally Relevant Stimulus Displacements in Egocentric Coordinates.

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    Feature selection has been extensively studied in the context of goal-directed behavior, where it is heavily driven by top-down factors. A more primitive version of this function is the detection of bottom-up changes in stimulus features in the environment. Indeed, the nervous system is tuned to detect fast-rising, intense stimuli that are likely to reflect threats, such as nociceptive somatosensory stimuli. These stimuli elicit large brain potentials maximal at the scalp vertex. When elicited by nociceptive laser stimuli, these responses are labeled laser-evoked potentials (LEPs). Although it has been shown that changes in stimulus modality and increases in stimulus intensity evoke large LEPs, it has yet to be determined whether stimulus displacements affect the amplitude of the main LEP waves (N1, N2, and P2). Here, in three experiments, we identified a set of rules that the human nervous system obeys to identify changes in the spatial location of a nociceptive stimulus. We showed that the N2 wave is sensitive to: (1) large displacements between consecutive stimuli in egocentric, but not somatotopic coordinates; and (2) displacements that entail a behaviorally relevant change in the stimulus location. These findings indicate that nociceptive-evoked vertex potentials are sensitive to behaviorally relevant changes in the location of a nociceptive stimulus with respect to the body, and that the hand is a particularly behaviorally important site

    Single-Event Upset Analysis and Protection in High Speed Circuits

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    The effect of single-event transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a single event upset (SEU) caused by particle strike on the internal nodes of a flip-flo
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