Estimating the strength of poker hands by integer linear programming techniques

We illustrate how Integer Linear Programming techniques can be applied to the popular game of poker Texas Hold'em in order to evaluate the strength of a hand. In particular, we give models aimed at (i) minimizing the number of features that a player should look at when estimating his winning probability (called his {em equity}); (ii) giving weights to such features so that the equity is approximated by the weighted sum of the selected features. We show that ten features or less are enough to estimate the equity of a hand with high precision

Algorithmic strategies for a fast exploration of the TSP 4 -OPT neighborhood

We describe an effective algorithm for exploring the 4 -OPT neighborhood for the Traveling Salesman Problem. 4 -OPT moves change a tour into another by replacing four of its edges. The best move can be found by a Θ (n4) algorithm by complete enumeration, but a Θ (n3) dynamic programming algorithm exists in the literature. Furthermore a Θ (n2) algorithm also exists for a particular subset of symmetric 4 -OPT moves. In this work we describe a new procedure which behaves, on average, slightly worse than a quadratic algorithm over all moves (estimated at O(n2.5)) and like a quadratic algorithm on the symmetric moves. Computational results are reported which show the effectiveness of our strategy compared to other algorithms for finding the best 4 -OPT move, and discuss the strength of the 4 -OPT neighborhood compared to 2- and 3 -OPT

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality of fault simulation and test generation tools using nominal IC parameters, we studied BF detection as a function of the standard deviation of parameters: results show that a single test vector cannot ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing null escape probability is upper-bounded with respect to variations of parameters, as verified by Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for low frequency testing. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability

Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits

This work extends to the switch level the verification and testing techniques based upon boolean satisfiability (SAT), so that SAT-based methodologies can be applied to circuits that cannot be well described at the gate level. The main achieved goal was to define a boolean model describing switch-level circuit operations as a SAT problem instance, to be applied to combinational equivalence checking and bridging-fault test generation. Results are provided for a set of combinational CMOS circuits, showing the feasibility of SAT-based verification and testing of switch-level circuits

How many test vectors we need to detect a bridging fault?

The growing dispersion of ICs' parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC's. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC's parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks

Virtual Simulation of Distributed IP-Based Designs

JavaCAD, an Internet-based tool with a secure client-server architecture, lets designers perform functional simulation, fault simulation, and cost estimation of circuits containing IP components. It also ensures IP protection for both IP vendors and users, and provides seamless transition between IP evaluation and purchase